From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qk1-x732.google.com (mail-qk1-x732.google.com [IPv6:2607:f8b0:4864:20::732]) by sourceware.org (Postfix) with ESMTPS id B12513858CDA for ; Mon, 18 Jul 2022 06:28:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org B12513858CDA Received: by mail-qk1-x732.google.com with SMTP id n2so6702927qkk.8 for ; Sun, 17 Jul 2022 23:28:22 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=stzyOSmP4H78z17AaqBxSKCZETArPdlfbxj1Kp8BlLY=; b=ouPCdujnoXWLoyTiJ85Ib9AxVAOY1iRoE8CR9BI5P5g2/P8k6Kvo1ZN0bMgCu3wjW2 nuhCy7hvUQHicTpVzPS53z63Ozt7HvhRFkBy12qQDH8z/bE7EQhroJnP8ODmcFX2FXTl dviMCWjerIBDdxFJcwguBABFrFHCn66FvV5o0+3bqRbJUdOPNwYqbupNUWRXnZBD5rM4 RBt70cfngKj/JM4CZQjOG9kMhZSHi8TAAOB+0aSAJHkkf1n+rhUOlqNXWcX19FGv1/ra LchPufba1zNrVdpGzvCenNGtNiSjFCWl8JsI9ThTe8ofGWM1h1PBKa9FW+OhInw5PnwM epHA== X-Gm-Message-State: AJIora93yHpYDH5PPkkJvUb3rmfqfCtV1MDe55bnbpeI1DOCqYOyta+B g4Qgwyi+1U7RIeHX7CQmoElgB7SE2Tw+9S8YUHgyHYzW8KI= X-Google-Smtp-Source: AGRyM1v3y3K19IOcrudQpd4BRgrVj0ISmeydJIsCJDa1JX2PBd20/vYaICMgH0/Gm0YgeUBLUFoT1g+UfoCTRR6aN9g= X-Received: by 2002:a05:620a:2619:b0:6b5:eddf:ef8e with SMTP id z25-20020a05620a261900b006b5eddfef8emr1384092qko.674.1658125702026; Sun, 17 Jul 2022 23:28:22 -0700 (PDT) MIME-Version: 1.0 References: <20220718015935.66003-1-hongtao.liu@intel.com> In-Reply-To: <20220718015935.66003-1-hongtao.liu@intel.com> From: Uros Bizjak Date: Mon, 18 Jul 2022 08:28:11 +0200 Message-ID: Subject: Re: [PATCH] Extend 16/32-bit vector bit_op patterns with (m,0,i)(vertical) alternative. To: liuhongt Cc: "gcc-patches@gcc.gnu.org" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 18 Jul 2022 06:28:24 -0000 On Mon, Jul 18, 2022 at 3:59 AM liuhongt wrote: > > And split it after reload. > > >IMO, the only case it is worth adding is a direct immediate store to > >memory, which HJ recently added. > > Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. > Ok for trunk? > > gcc/ChangeLog: > > PR target/106038 > * config/i386/mmx.md (3): Extend to AND mem,imm, > and adjust below define_split. > (mmxinsnmode): New mode attribute. > (*mov_imm): Refactor with mmxinsnmode. > * config/i386/predicates.md > (register_or_x86_64_const_vector_operand): New predicate. > > gcc/testsuite/ChangeLog: > > * gcc.target/i386/pr106038-1.c: New test. > --- > gcc/config/i386/mmx.md | 58 +++++++++++----------- > gcc/config/i386/predicates.md | 4 ++ > gcc/testsuite/gcc.target/i386/pr106038-1.c | 27 ++++++++++ > 3 files changed, 60 insertions(+), 29 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/i386/pr106038-1.c > > diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md > index 3294c1e6274..fbcb34d4395 100644 > --- a/gcc/config/i386/mmx.md > +++ b/gcc/config/i386/mmx.md > @@ -86,6 +86,14 @@ (define_mode_attr mmxvecsize > [(V8QI "b") (V4QI "b") (V2QI "b") > (V4HI "w") (V2HI "w") (V2SI "d") (V1DI "q")]) > > +;; Mapping to same size integral mode. > +(define_mode_attr mmxinsnmode > + [(V8QI "DI") (V4QI "SI") (V2QI "HI") > + (V4HI "DI") (V2HI "SI") > + (V2SI "DI") > + (V4HF "DI") (V2HF "SI") > + (V2SF "DI")]) > + > (define_mode_attr mmxdoublemode > [(V8QI "V8HI") (V4HI "V4SI")]) > > @@ -350,22 +358,7 @@ (define_insn_and_split "*mov_imm" > HOST_WIDE_INT val = ix86_convert_const_vector_to_integer (operands[1], > mode); > operands[1] = GEN_INT (val); > - machine_mode mode; > - switch (GET_MODE_SIZE (mode)) > - { > - case 2: > - mode = HImode; > - break; > - case 4: > - mode = SImode; > - break; > - case 8: > - mode = DImode; > - break; > - default: > - gcc_unreachable (); > - } > - operands[0] = lowpart_subreg (mode, operands[0], mode); > + operands[0] = lowpart_subreg (mode, operands[0], mode); > }) > > ;; For TARGET_64BIT we always round up to 8 bytes. > @@ -2975,32 +2968,39 @@ (define_insn "*mmx_3" > (set_attr "mode" "DI,TI,TI,TI")]) > > (define_insn "3" > - [(set (match_operand:VI_16_32 0 "register_operand" "=?r,x,x,v") > + [(set (match_operand:VI_16_32 0 "nonimmediate_operand" "=?r,m,x,x,v") > (any_logic:VI_16_32 > - (match_operand:VI_16_32 1 "register_operand" "%0,0,x,v") > - (match_operand:VI_16_32 2 "register_operand" "r,x,x,v"))) > + (match_operand:VI_16_32 1 "nonimmediate_operand" "%0,0,0,x,v") > + (match_operand:VI_16_32 2 "register_or_x86_64_const_vector_operand" "r,i,x,x,v"))) > (clobber (reg:CC FLAGS_REG))] > "" You will need ix86_binary_operator_ok insn constraint here with corresponding expander using ix86_fixup_binary_operands_no_copy to prepare insn operands. > "#" > - [(set_attr "isa" "*,sse2_noavx,avx,avx512vl") > - (set_attr "type" "alu,sselog,sselog,sselog") > - (set_attr "mode" "SI,TI,TI,TI")]) > + [(set_attr "isa" "*,*,sse2_noavx,avx,avx512vl") > + (set_attr "type" "alu,alu,sselog,sselog,sselog") > + (set_attr "mode" "SI,SI,TI,TI,TI")]) > > (define_split > - [(set (match_operand:VI_16_32 0 "general_reg_operand") > + [(set (match_operand:VI_16_32 0 "nonimmediate_gr_operand") > (any_logic:VI_16_32 > - (match_operand:VI_16_32 1 "general_reg_operand") > - (match_operand:VI_16_32 2 "general_reg_operand"))) > + (match_operand:VI_16_32 1 "nonimmediate_gr_operand") > + (match_operand:VI_16_32 2 "register_or_x86_64_const_vector_operand"))) > (clobber (reg:CC FLAGS_REG))] > "reload_completed" > [(parallel > [(set (match_dup 0) > - (any_logic:SI (match_dup 1) (match_dup 2))) > + (any_logic: (match_dup 1) (match_dup 2))) > (clobber (reg:CC FLAGS_REG))])] > { > - operands[2] = lowpart_subreg (SImode, operands[2], mode); > - operands[1] = lowpart_subreg (SImode, operands[1], mode); > - operands[0] = lowpart_subreg (SImode, operands[0], mode); > + if (GET_CODE (operands[2]) == CONST_VECTOR) Please use if (!register_operand (operands[2], mode)) instead. Uros. > + { > + HOST_WIDE_INT val = ix86_convert_const_vector_to_integer (operands[2], > + mode); > + operands[2] = GEN_INT (val); > + } > + else > + operands[2] = lowpart_subreg (mode, operands[2], mode); > + operands[1] = lowpart_subreg (mode, operands[1], mode); > + operands[0] = lowpart_subreg (mode, operands[0], mode); > }) > > (define_split > diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md > index c71c453cceb..5f63a7d52f5 100644 > --- a/gcc/config/i386/predicates.md > +++ b/gcc/config/i386/predicates.md > @@ -1205,6 +1205,10 @@ (define_predicate "x86_64_const_vector_operand" > return trunc_int_for_mode (val, SImode) == val; > }) > > +(define_predicate "register_or_x86_64_const_vector_operand" > + (ior (match_operand 0 "register_operand") > + (match_operand 0 "x86_64_const_vector_operand"))) > + > ;; Return true when OP is nonimmediate or standard SSE constant. > (define_predicate "nonimmediate_or_sse_const_operand" > (ior (match_operand 0 "nonimmediate_operand") > diff --git a/gcc/testsuite/gcc.target/i386/pr106038-1.c b/gcc/testsuite/gcc.target/i386/pr106038-1.c > new file mode 100644 > index 00000000000..bb52385c8a5 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/pr106038-1.c > @@ -0,0 +1,27 @@ > +/* { dg-do compile } */ > +/* { dg-options "-msse2 -O2" } */ > +/* { dg-final { scan-assembler-not "xmm" } } */ > + > +void > +foo3 (char* a, char* __restrict b) > +{ > + a[0] &= 1; > + a[1] &= 2; > + a[2] &= 3; > + a[3] &= 3; > +} > + > +void > +foo4 (char* a, char* __restrict b) > +{ > + a[0] &= 1; > + a[1] &= 2; > +} > + > + > +void > +foo1 (short* a, short* __restrict b) > +{ > + a[0] &= 1; > + a[1] &= 2; > +} > -- > 2.18.1 >