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From: Uros Bizjak <ubizjak@gmail.com>
To: Hongtao Liu <crazylht@gmail.com>
Cc: "H.J. Lu" <hjl.tools@gmail.com>,
	Hongtao Liu <hongtao.liu@intel.com>,
	 "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Subject: Re: [PATCH] x86: Compile CPUID functions with -mgeneral-regs-only
Date: Fri, 25 Jun 2021 09:49:56 +0200	[thread overview]
Message-ID: <CAFULd4Zj1wAhoiy=e1p-yHFi02ZjXNmwAfdxOtjem+nHDN7JwA@mail.gmail.com> (raw)
In-Reply-To: <CAMZc-bxxNx7sSXh=t=yFKEiacsFdNQDLnYokkiBoeoZQcwwnow@mail.gmail.com>

On Fri, Jun 25, 2021 at 4:51 AM Hongtao Liu <crazylht@gmail.com> wrote:
>
> On Fri, Jun 25, 2021 at 12:13 AM Uros Bizjak via Gcc-patches
> <gcc-patches@gcc.gnu.org> wrote:
> >
> > On Thu, Jun 24, 2021 at 2:12 PM H.J. Lu <hjl.tools@gmail.com> wrote:
> > >
> > > CPUID functions are used to detect CPU features.  If vector ISAs
> > > are enabled, compiler is free to use them in these functions.  Add
> > > __attribute__ ((target("general-regs-only"))) to CPUID functions
> > > to avoid vector instructions.
> >
> > These functions are intended to be inlined, so how does target
> > attribute affect inlining?
> I guess w/ -O0. they may not be inlined, that's why H.J adds those
> attributes to those functions.

The problem is not with these functions, but with surrounding checks
for cpuid features. These checks are implemented with logic
instructions, and nothing prevents RA from allocating mask registers,
and consequently mask insn is emitted. Regarding mentioned functions,
cpuid insn pattern has four GPR single-reg constraints, so mask
registers can't be allocated here.

> pr96814.dump:
> 0804aa40 <main>:
>  804aa40: 8d 4c 24 04          lea    0x4(%esp),%ecx
> ...
>  804aa63: 6a 07                push   $0x7
>  804aa65: e8 e0 e7 ff ff        call   804924a <__get_cpuid_count>
>
> Also we need to add a target attribute to avx512f_os_support (), and
> that would be enough to fix the AVX512 part.
>
> Moreover, all check functions in below files may also need to deal with:
> adx-check.h
> aes-avx-check.h
> aes-check.h
> amx-check.h
> attr-nocf-check-1a.c
> attr-nocf-check-3a.c
> avx2-check.h
> avx2-vpop-check.h
> avx512bw-check.h
> avx512-check.h
> avx512dq-check.h
> avx512er-check.h
> avx512f-check.h
> avx512vl-check.h
> avx-check.h
> bmi2-check.h
> bmi-check.h
> cf_check-1.c
> cf_check-2.c
> cf_check-3.c
> cf_check-4.c
> cf_check-5.c
> f16c-check.h
> fma4-check.h
> fma-check.h
> isa-check.h
> lzcnt-check.h
> m128-check.h
> m256-check.h
> m512-check.h
> mmx-3dnow-check.h
> mmx-check.h
> pclmul-avx-check.h
> pclmul-check.h
> pr39315-check.c
> rtm-check.h
> sha-check.h
> spellcheck-options-1.c
> spellcheck-options-2.c
> spellcheck-options-3.c
> spellcheck-options-4.c
> spellcheck-options-5.c
> sse2-check.h
> sse3-check.h
> sse4_1-check.h
> sse4_2-check.h
> sse4a-check.h
> sse-check.h
> ssse3-check.h
> stack-check-11.c
> stack-check-12.c
> stack-check-17.c
> stack-check-18.c
> stack-check-19.c
> xop-check.h

True, but this would just paper over the real problem. Now, it is
expected that the user decorates the function that checks CPUID
features with the target attribute. I'm not sure if this is OK.

Uros.

  reply	other threads:[~2021-06-25  7:50 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-24 12:12 H.J. Lu
2021-06-24 12:35 ` Richard Biener
2021-06-24 12:41   ` H.J. Lu
2021-06-24 12:47     ` Richard Biener
2021-06-24 13:00       ` H.J. Lu
2021-06-24 16:12 ` Uros Bizjak
2021-06-24 18:00   ` H.J. Lu
2021-06-25  2:56   ` Hongtao Liu
2021-06-25  7:49     ` Uros Bizjak [this message]
2021-06-25 12:39       ` [PATCH v2] x86: Check AVX512 without mask instructions H.J. Lu
2021-07-14 12:27         ` PING^1 " H.J. Lu
2021-07-26  3:33           ` Hongtao Liu
2021-07-30 10:02             ` Uros Bizjak

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