From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [IPv6:2a00:1450:4864:20::535]) by sourceware.org (Postfix) with ESMTPS id A452A3858C62 for ; Thu, 31 Aug 2023 10:06:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A452A3858C62 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ed1-x535.google.com with SMTP id 4fb4d7f45d1cf-52a06f5f556so781414a12.2 for ; Thu, 31 Aug 2023 03:06:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1693476411; x=1694081211; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=SXo24nn5xmfgTOUia9bol8OYMouy6knuJ/a3/d9ghHg=; b=iKle4DrFl+l8BOsBG8j6rVn0b+puRGW+T120Ei74cpMXxBDBNdN6BP4RbbLgCC5Ld6 9be2ktP1BkkzInTPT6HlasHuL147/9iUh87ehjR0t6cjAYnfTWplPs39tvR1YffgxZiP m6xhm9SocC560uYB3uFGUDT4tFJx1KI+6myadgmCA8pIK7FDRfwx8aqRTe7xpsHbP/hD Ij1pcfuL9++Eadr6ibzTvH2kNiAir18uVx80NKn1ekrQcNzeVNc+YfA53J7NlkE7DiDw kZTZ6UPjQKDsft+Y6BB/3R08tHNzTzWCedSfVsliuMbt1s2DPpQvOOyizTkUm4XtEWAu p3zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693476411; x=1694081211; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SXo24nn5xmfgTOUia9bol8OYMouy6knuJ/a3/d9ghHg=; b=Aylzyo27MFdfWw8PiIThG9xnlvnHbfcNui446Q/nKBaGxxkzo2+Dxq9Cc0T/ingc1S vvXtKWDV6/vtX7e9dLOCWHb2w5+FzHcK2Tf4BuQTf+K348xAU3jrOiKVsUNJzw6y3g2G DulFWLl6N0xeXhOYE0cqmgtf3LHNgRVhg9uMPi0d7lOchhahEwmINgFmN0udbnuqjBSY ao0oBrr62mW6p7MFVyCeAN4W+x47qCtRgMlqMMNgwguaiyk09KjouQzt554iA5YBVKMt g60URz07N4W8hvO802f5cql+soJI4VTiAJrJPRzwu6p9Ivwijy+cf7HLdN4876Q2zrc4 14yA== X-Gm-Message-State: AOJu0Yx+L8tihCZErKPTCyVl+KxLx3pawfRljDYqbSJtcPEj863E59dy AsrTyNY736HQeor7F2nSHDzW3hE7Eebr2gIhSZJca1zcnkw= X-Google-Smtp-Source: AGHT+IEO7nqL3yKv3l57Y2zkJsMP16pJsjJY6j/Z/bKKdiCUH5owkapQiAbvr0yOPSUwmf5yLPUI30V6GRddjB3vI00= X-Received: by 2002:a05:6402:1510:b0:527:fa8d:d3ff with SMTP id f16-20020a056402151000b00527fa8dd3ffmr3569838edw.6.1693476411012; Thu, 31 Aug 2023 03:06:51 -0700 (PDT) MIME-Version: 1.0 References: <20230831082024.314097-1-hongyu.wang@intel.com> <20230831082024.314097-10-hongyu.wang@intel.com> In-Reply-To: <20230831082024.314097-10-hongyu.wang@intel.com> From: Uros Bizjak Date: Thu, 31 Aug 2023 12:06:39 +0200 Message-ID: Subject: Re: [PATCH 09/13] [APX EGPR] Handle legacy insn that only support GPR16 (1/5) To: Hongyu Wang Cc: gcc-patches@gcc.gnu.org, hongtao.liu@intel.com, hubicka@ucw.cz, vmakarov@redhat.com, jakub@redhat.com, Kong Lingling Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, Aug 31, 2023 at 10:20=E2=80=AFAM Hongyu Wang wrote: > > From: Kong Lingling > > These legacy insn in opcode map0/1 only support GPR16, > and do not have vex/evex counterpart, directly adjust constraints and > add gpr32 attr to patterns. > > insn list: > 1. xsave/xsave64, xrstor/xrstor64 > 2. xsaves/xsaves64, xrstors/xrstors64 > 3. xsavec/xsavec64 > 4. xsaveopt/xsaveopt64 > 5. fxsave64/fxrstor64 IMO, instructions should be handled with a reversed approach. Add "h" constraint (and memory constraint that can handle EGPR) to instructions that CAN use EGPR (together with a relevant "enabled" attribute. We have had the same approach with "x" to "v" transition with SSE registers. If we "forgot" to add "v" to the instruction, it still worked, but not to its full potential w.r.t available registers. Uros. > > gcc/ChangeLog: > > * config/i386/i386.md (): Set attr gpr32 0 and constraint > Bt. > (_rex64): Likewise. > (_rex64): Likewise. > (64): Likewise. > (fxsave64): Likewise. > (fxstore64): Likewise. > > gcc/testsuite/ChangeLog: > > * lib/target-supports.exp: Add apxf check. > * gcc.target/i386/apx-legacy-insn-check-norex2.c: New test. > * gcc.target/i386/apx-legacy-insn-check-norex2-asm.c: New assembl= er test. > --- > gcc/config/i386/i386.md | 18 +++++++---- > .../i386/apx-legacy-insn-check-norex2-asm.c | 5 ++++ > .../i386/apx-legacy-insn-check-norex2.c | 30 +++++++++++++++++++ > gcc/testsuite/lib/target-supports.exp | 10 +++++++ > 4 files changed, 57 insertions(+), 6 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/i386/apx-legacy-insn-check-n= orex2-asm.c > create mode 100644 gcc/testsuite/gcc.target/i386/apx-legacy-insn-check-n= orex2.c > > diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md > index b9eaea78f00..83ad01b43c1 100644 > --- a/gcc/config/i386/i386.md > +++ b/gcc/config/i386/i386.md > @@ -25626,11 +25626,12 @@ (define_insn "fxsave" > (symbol_ref "ix86_attr_length_address_default (insn) + 3"))]) > > (define_insn "fxsave64" > - [(set (match_operand:BLK 0 "memory_operand" "=3Dm") > + [(set (match_operand:BLK 0 "memory_operand" "=3DBt") > (unspec_volatile:BLK [(const_int 0)] UNSPECV_FXSAVE64))] > "TARGET_64BIT && TARGET_FXSR" > "fxsave64\t%0" > [(set_attr "type" "other") > + (set_attr "gpr32" "0") > (set_attr "memory" "store") > (set (attr "length") > (symbol_ref "ix86_attr_length_address_default (insn) + 4"))]) > @@ -25646,11 +25647,12 @@ (define_insn "fxrstor" > (symbol_ref "ix86_attr_length_address_default (insn) + 3"))]) > > (define_insn "fxrstor64" > - [(unspec_volatile [(match_operand:BLK 0 "memory_operand" "m")] > + [(unspec_volatile [(match_operand:BLK 0 "memory_operand" "Bt")] > UNSPECV_FXRSTOR64)] > "TARGET_64BIT && TARGET_FXSR" > "fxrstor64\t%0" > [(set_attr "type" "other") > + (set_attr "gpr32" "0") > (set_attr "memory" "load") > (set (attr "length") > (symbol_ref "ix86_attr_length_address_default (insn) + 4"))]) > @@ -25704,7 +25706,7 @@ (define_insn "" > (symbol_ref "ix86_attr_length_address_default (insn) + 3"))]) > > (define_insn "_rex64" > - [(set (match_operand:BLK 0 "memory_operand" "=3Dm") > + [(set (match_operand:BLK 0 "memory_operand" "=3DBt") > (unspec_volatile:BLK > [(match_operand:SI 1 "register_operand" "a") > (match_operand:SI 2 "register_operand" "d")] > @@ -25713,11 +25715,12 @@ (define_insn "_rex64" > "\t%0" > [(set_attr "type" "other") > (set_attr "memory" "store") > + (set_attr "gpr32" "0") > (set (attr "length") > (symbol_ref "ix86_attr_length_address_default (insn) + 3"))]) > > (define_insn "" > - [(set (match_operand:BLK 0 "memory_operand" "=3Dm") > + [(set (match_operand:BLK 0 "memory_operand" "=3DBt") > (unspec_volatile:BLK > [(match_operand:SI 1 "register_operand" "a") > (match_operand:SI 2 "register_operand" "d")] > @@ -25726,6 +25729,7 @@ (define_insn "" > "\t%0" > [(set_attr "type" "other") > (set_attr "memory" "store") > + (set_attr "gpr32" "0") > (set (attr "length") > (symbol_ref "ix86_attr_length_address_default (insn) + 4"))]) > > @@ -25743,7 +25747,7 @@ (define_insn "" > > (define_insn "_rex64" > [(unspec_volatile:BLK > - [(match_operand:BLK 0 "memory_operand" "m") > + [(match_operand:BLK 0 "memory_operand" "Bt") > (match_operand:SI 1 "register_operand" "a") > (match_operand:SI 2 "register_operand" "d")] > ANY_XRSTOR)] > @@ -25751,12 +25755,13 @@ (define_insn "_rex64" > "\t%0" > [(set_attr "type" "other") > (set_attr "memory" "load") > + (set_attr "gpr32" "0") > (set (attr "length") > (symbol_ref "ix86_attr_length_address_default (insn) + 3"))]) > > (define_insn "64" > [(unspec_volatile:BLK > - [(match_operand:BLK 0 "memory_operand" "m") > + [(match_operand:BLK 0 "memory_operand" "Bt") > (match_operand:SI 1 "register_operand" "a") > (match_operand:SI 2 "register_operand" "d")] > ANY_XRSTOR64)] > @@ -25764,6 +25769,7 @@ (define_insn "64" > "64\t%0" > [(set_attr "type" "other") > (set_attr "memory" "load") > + (set_attr "gpr32" "0") > (set (attr "length") > (symbol_ref "ix86_attr_length_address_default (insn) + 4"))]) > > diff --git a/gcc/testsuite/gcc.target/i386/apx-legacy-insn-check-norex2-a= sm.c b/gcc/testsuite/gcc.target/i386/apx-legacy-insn-check-norex2-asm.c > new file mode 100644 > index 00000000000..7ecc861435f > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/apx-legacy-insn-check-norex2-asm.c > @@ -0,0 +1,5 @@ > +/* { dg-do assemble { target apxf } } */ > +/* { dg-options "-O1 -mapxf -m64 -DDTYPE32" } */ > + > +#include "apx-legacy-insn-check-norex2.c" > + > diff --git a/gcc/testsuite/gcc.target/i386/apx-legacy-insn-check-norex2.c= b/gcc/testsuite/gcc.target/i386/apx-legacy-insn-check-norex2.c > new file mode 100644 > index 00000000000..1e5450dfb73 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/apx-legacy-insn-check-norex2.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O3 -mapxf -m64 -DDTYPE32" } */ > + > +#include > + > +typedef unsigned int u32; > +typedef unsigned long long u64; > + > +#ifndef DTYPE32 > +#define DTYPE32 > +#endif > + > +#ifdef DTYPE32 > +typedef u32 DTYPE; > +#endif > + > +__attribute__((target("xsave,fxsr"))) > +void legacy_test () > +{ > + register DTYPE* val __asm__("r16"); > + _xsave64 (val, 1); > + _xrstor64 (val, 1); > + _fxsave64 (val); > + _fxrstor64 (val); > +} > + > +/* { dg-final { scan-assembler-not "xsave64\[ \\t]+\\\.\\\*r\(1\[6-9\]\|= 2\[0-9\]|30\|31\)" } } */ > +/* { dg-final { scan-assembler-not "xrstor64\[ \\t]+\\\.\\\*r\(1\[6-9\]\= |2\[0-9\]|30\|31\)" } } */ > +/* { dg-final { scan-assembler-not "fxsave64\[ \\t]+\\\.\\\*r\(1\[6-9\]\= |2\[0-9\]|30\|31\)" } } */ > +/* { dg-final { scan-assembler-not "fxrstor64\[ \\t]+\\\.\\\*r\(1\[6-9\]= \|2\[0-9\]|30\|31\)" } } */ > diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/ta= rget-supports.exp > index d353cc0aaf0..6359408542a 100644 > --- a/gcc/testsuite/lib/target-supports.exp > +++ b/gcc/testsuite/lib/target-supports.exp > @@ -9938,6 +9938,16 @@ proc check_effective_target_sm4 { } { > } "-msm4" ] > } > > +proc check_effective_target_apxf { } { > + return [check_no_compiler_messages apxf object { > + void > + foo () > + { > + __asm__ volatile ("add\t%%r16, %%r31" ::); > + } > + } "-mapxf" ] > +} > + > # Return 1 if sse instructions can be compiled. > proc check_effective_target_sse { } { > return [check_no_compiler_messages sse object { > -- > 2.31.1 >