From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qt1-x830.google.com (mail-qt1-x830.google.com [IPv6:2607:f8b0:4864:20::830]) by sourceware.org (Postfix) with ESMTPS id E64193858D28 for ; Thu, 21 Jul 2022 05:55:18 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E64193858D28 Received: by mail-qt1-x830.google.com with SMTP id r21so569249qtn.11 for ; Wed, 20 Jul 2022 22:55:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=lAamUawOnFFpY5BBjz29Zzkw+hfsJZc9z1vLVHqfm2o=; b=PJIz40+NaiqD3cI0ggGkPiYxqNlLuoFcI4fNQ//a2ATWIVCAZ4bYV0fmMuVmFhJcR8 uVtCfzj0OqedCHIS3DZ4uZtHLTZbMS9MUPmNMlTE/Wp7vic3DhT/t3NPuaPgS8XqrzHF G1YC4qK8Iy7zBZ/v1PioLb62i81wC/h+8sCQOe9S6ymgjn5ynUflOqaa0Ikwp1dgvzDr Z2fovToMzI4a1RTQR9lVwptTryl7+F7CrI0FwjrQSIG1I/vxSHdqagxI7qf5hHYwTsci OfLz2alg1XnXBauw+mzkkGWMu/JLNfB9TpXdBm3Im4DkE3n1qc+LCbVLAZa42i4W1m5v ClUQ== X-Gm-Message-State: AJIora+YQVc4ZtXfXUq0wvJRLLt2HfTXTzqxZy25qSmb//YliZ/TQvyg B1ux88U/MvT5cbVV4x0keK6RiVde26rILGbiKCI0HbF/gRg= X-Google-Smtp-Source: AGRyM1u6DX4hChjB4v1iFyJucWVnvFyrxofsbhTWMQShoLmMhfTLtvuxxTbILQFnFtuxxfmtlKaLnTKaE36JzM5bKPI= X-Received: by 2002:a05:622a:204:b0:31f:3bb:3294 with SMTP id b4-20020a05622a020400b0031f03bb3294mr7810687qtx.436.1658382918265; Wed, 20 Jul 2022 22:55:18 -0700 (PDT) MIME-Version: 1.0 References: <20220721051841.13832-1-hongtao.liu@intel.com> In-Reply-To: <20220721051841.13832-1-hongtao.liu@intel.com> From: Uros Bizjak Date: Thu, 21 Jul 2022 07:55:06 +0200 Message-ID: Subject: Re: [PATCH V3] Extend 16/32-bit vector bit_op patterns with (m, 0, i) alternative. To: liuhongt Cc: "gcc-patches@gcc.gnu.org" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-9.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jul 2022 05:55:20 -0000 On Thu, Jul 21, 2022 at 7:19 AM liuhongt wrote: > > And split it after reload. > > gcc/ChangeLog: > > PR target/106038 > * config/i386/mmx.md (3): New define_expand, it's > original "3". > (*3): New define_insn, it's original > "3" be extended to handle memory and immediate > operand with ix86_binary_operator_ok. Also adjust define_split > after it. > (mmxinsnmode): New mode attribute. > (*mov_imm): Refactor with mmxinsnmode. > * config/i386/predicates.md > (register_or_x86_64_const_vector_operand): New predicate. > > gcc/testsuite/ChangeLog: > > * gcc.target/i386/pr106038-1.c: New test. OK. Thanks, Uros. > --- > gcc/config/i386/mmx.md | 70 ++++++++++++---------- > gcc/config/i386/predicates.md | 4 ++ > gcc/testsuite/gcc.target/i386/pr106038-1.c | 27 +++++++++ > 3 files changed, 70 insertions(+), 31 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/i386/pr106038-1.c > > diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md > index 3294c1e6274..dda4b43f5c1 100644 > --- a/gcc/config/i386/mmx.md > +++ b/gcc/config/i386/mmx.md > @@ -86,6 +86,14 @@ (define_mode_attr mmxvecsize > [(V8QI "b") (V4QI "b") (V2QI "b") > (V4HI "w") (V2HI "w") (V2SI "d") (V1DI "q")]) > > +;; Mapping to same size integral mode. > +(define_mode_attr mmxinsnmode > + [(V8QI "DI") (V4QI "SI") (V2QI "HI") > + (V4HI "DI") (V2HI "SI") > + (V2SI "DI") > + (V4HF "DI") (V2HF "SI") > + (V2SF "DI")]) > + > (define_mode_attr mmxdoublemode > [(V8QI "V8HI") (V4HI "V4SI")]) > > @@ -350,22 +358,7 @@ (define_insn_and_split "*mov_imm" > HOST_WIDE_INT val = ix86_convert_const_vector_to_integer (operands[1], > mode); > operands[1] = GEN_INT (val); > - machine_mode mode; > - switch (GET_MODE_SIZE (mode)) > - { > - case 2: > - mode = HImode; > - break; > - case 4: > - mode = SImode; > - break; > - case 8: > - mode = DImode; > - break; > - default: > - gcc_unreachable (); > - } > - operands[0] = lowpart_subreg (mode, operands[0], mode); > + operands[0] = lowpart_subreg (mode, operands[0], mode); > }) > > ;; For TARGET_64BIT we always round up to 8 bytes. > @@ -2974,33 +2967,48 @@ (define_insn "*mmx_3" > (set_attr "type" "mmxadd,sselog,sselog,sselog") > (set_attr "mode" "DI,TI,TI,TI")]) > > -(define_insn "3" > - [(set (match_operand:VI_16_32 0 "register_operand" "=?r,x,x,v") > +(define_expand "3" > + [(set (match_operand:VI_16_32 0 "nonimmediate_operand") > (any_logic:VI_16_32 > - (match_operand:VI_16_32 1 "register_operand" "%0,0,x,v") > - (match_operand:VI_16_32 2 "register_operand" "r,x,x,v"))) > - (clobber (reg:CC FLAGS_REG))] > + (match_operand:VI_16_32 1 "nonimmediate_operand") > + (match_operand:VI_16_32 2 "nonimmediate_or_x86_64_const_vector_operand")))] > "" > + "ix86_expand_binary_operator (, mode, operands); DONE;") > + > +(define_insn "*3" > + [(set (match_operand:VI_16_32 0 "nonimmediate_operand" "=?r,m,x,x,v") > + (any_logic:VI_16_32 > + (match_operand:VI_16_32 1 "nonimmediate_operand" "%0,0,0,x,v") > + (match_operand:VI_16_32 2 "nonimmediate_or_x86_64_const_vector_operand" "r,i,x,x,v"))) > + (clobber (reg:CC FLAGS_REG))] > + "ix86_binary_operator_ok (, mode, operands)" > "#" > - [(set_attr "isa" "*,sse2_noavx,avx,avx512vl") > - (set_attr "type" "alu,sselog,sselog,sselog") > - (set_attr "mode" "SI,TI,TI,TI")]) > + [(set_attr "isa" "*,*,sse2_noavx,avx,avx512vl") > + (set_attr "type" "alu,alu,sselog,sselog,sselog") > + (set_attr "mode" "SI,SI,TI,TI,TI")]) > > (define_split > - [(set (match_operand:VI_16_32 0 "general_reg_operand") > + [(set (match_operand:VI_16_32 0 "nonimmediate_gr_operand") > (any_logic:VI_16_32 > - (match_operand:VI_16_32 1 "general_reg_operand") > - (match_operand:VI_16_32 2 "general_reg_operand"))) > + (match_operand:VI_16_32 1 "nonimmediate_gr_operand") > + (match_operand:VI_16_32 2 "reg_or_const_vector_operand"))) > (clobber (reg:CC FLAGS_REG))] > "reload_completed" > [(parallel > [(set (match_dup 0) > - (any_logic:SI (match_dup 1) (match_dup 2))) > + (any_logic: (match_dup 1) (match_dup 2))) > (clobber (reg:CC FLAGS_REG))])] > { > - operands[2] = lowpart_subreg (SImode, operands[2], mode); > - operands[1] = lowpart_subreg (SImode, operands[1], mode); > - operands[0] = lowpart_subreg (SImode, operands[0], mode); > + if (!register_operand (operands[2], mode)) > + { > + HOST_WIDE_INT val = ix86_convert_const_vector_to_integer (operands[2], > + mode); > + operands[2] = GEN_INT (val); > + } > + else > + operands[2] = lowpart_subreg (mode, operands[2], mode); > + operands[1] = lowpart_subreg (mode, operands[1], mode); > + operands[0] = lowpart_subreg (mode, operands[0], mode); > }) > > (define_split > diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md > index c71c453cceb..73dfd46bf90 100644 > --- a/gcc/config/i386/predicates.md > +++ b/gcc/config/i386/predicates.md > @@ -1205,6 +1205,10 @@ (define_predicate "x86_64_const_vector_operand" > return trunc_int_for_mode (val, SImode) == val; > }) > > +(define_predicate "nonimmediate_or_x86_64_const_vector_operand" > + (ior (match_operand 0 "nonimmediate_operand") > + (match_operand 0 "x86_64_const_vector_operand"))) > + > ;; Return true when OP is nonimmediate or standard SSE constant. > (define_predicate "nonimmediate_or_sse_const_operand" > (ior (match_operand 0 "nonimmediate_operand") > diff --git a/gcc/testsuite/gcc.target/i386/pr106038-1.c b/gcc/testsuite/gcc.target/i386/pr106038-1.c > new file mode 100644 > index 00000000000..bb52385c8a5 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/pr106038-1.c > @@ -0,0 +1,27 @@ > +/* { dg-do compile } */ > +/* { dg-options "-msse2 -O2" } */ > +/* { dg-final { scan-assembler-not "xmm" } } */ > + > +void > +foo3 (char* a, char* __restrict b) > +{ > + a[0] &= 1; > + a[1] &= 2; > + a[2] &= 3; > + a[3] &= 3; > +} > + > +void > +foo4 (char* a, char* __restrict b) > +{ > + a[0] &= 1; > + a[1] &= 2; > +} > + > + > +void > +foo1 (short* a, short* __restrict b) > +{ > + a[0] &= 1; > + a[1] &= 2; > +} > -- > 2.18.1 >