Hello!

Attached patch allows memory operands for btr/bts and btc
instructions.  The previous comment was wrong, these instructions do
not enforce atomic operations with memory operand without "lock"
prefix. Instructions in its RMW form with immediate operand are not
slower than corresponding logic instructions.

(When variable count operand is used with RMW form, these instructions
are considerably slower, since they can address full 32bit address
range from their base operand.)

2017-08-16  Uros Bizjak  <ubizjak@gmail.com>

    PR target/46091
    * config/i386/i386.md (*anddi_1_btr): Change predicates of
    operand 0 and operand 1 to nomimmediate_operand. Add "m" constraint.
    Add ix86_binary_operator_ok to insn constraint.
    (*iordi_1_bts): Ditto.
    (*xordi_1_btc): Ditto.
    (*btsq): Change predicate of operand 0 to nonimmediate_operand.
    Update corresponding peephole2 pattern.
    (*btrq): Ditto.
    (*btcq): Ditto.

testsuite/ChangeLog:

2017-08-16  Uros Bizjak  <ubizjak@gmail.com>

    PR target/46091
    * gcc.target/i386/pr46091-1.c: Update scan-assembler-times.
    (testm): New test function.
    * gcc.target/i386/pr46091-2.c: Ditto.
    * gcc.target/i386/pr46091-3.c: Ditto.

Patch was bootstrapped and regression tested on x86_64-linux-gnu.

Committed to mainline SVN.

Uros.