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* [PATCH] target/100312 - make x86 masked load builtins pure
@ 2021-04-28 11:02 Richard Biener
  2021-04-28 11:23 ` Uros Bizjak
  0 siblings, 1 reply; 8+ messages in thread
From: Richard Biener @ 2021-04-28 11:02 UTC (permalink / raw)
  To: gcc-patches; +Cc: jakub, ubizjak

This arranges for the x86 AVX and AVX2 masked load builtins to be
pure to enable dead code elimination and more appropriate alias
analysis.

Bootstrapped and tested on x86_64-unknown-linux-gnu.  OK for trunk?

Thanks,
Richard.

2021-04-28  Richard Biener  <rguenther@suse.de>

	PR target/100312
	* config/i386/i386-builtin.def (IX86_BUILTIN_MASKLOADPD,
	IX86_BUILTIN_MASKLOADPS, IX86_BUILTIN_MASKLOADPD256,
	IX86_BUILTIN_MASKLOADPS256, IX86_BUILTIN_MASKLOADD,
	IX86_BUILTIN_MASKLOADQ, IX86_BUILTIN_MASKLOADD256,
	IX86_BUILTIN_MASKLOADQ256): Remove.
	* config/i386/i386-builtins.h (ix86_builtins): Add entries for
	IX86_BUILTIN_MASKLOADPD, IX86_BUILTIN_MASKLOADPS,
	IX86_BUILTIN_MASKLOADPD256, IX86_BUILTIN_MASKLOADPS256,
	IX86_BUILTIN_MASKLOADD, IX86_BUILTIN_MASKLOADQ,
	IX86_BUILTIN_MASKLOADD256, and IX86_BUILTIN_MASKLOADQ256.
	* config/i386/i386-builtins.c (ix86_init_mmx_sse_builtins):
	Initialize IX86_BUILTIN_MASKLOADPD, IX86_BUILTIN_MASKLOADPS,
	IX86_BUILTIN_MASKLOADPD256, IX86_BUILTIN_MASKLOADPS256,
	IX86_BUILTIN_MASKLOADD, IX86_BUILTIN_MASKLOADQ,
	IX86_BUILTIN_MASKLOADD256, and IX86_BUILTIN_MASKLOADQ256
	as pure builtins.
---
 gcc/config/i386/i386-builtin.def |  8 --------
 gcc/config/i386/i386-builtins.c  | 19 +++++++++++++++++++
 gcc/config/i386/i386-builtins.h  |  8 ++++++++
 3 files changed, 27 insertions(+), 8 deletions(-)

diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index 4dbd4f23647..dc0452de645 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -187,10 +187,6 @@ BDESC (OPTION_MASK_ISA_AVX, 0, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq25
 BDESC (OPTION_MASK_ISA_AVX, 0, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF)
 BDESC (OPTION_MASK_ISA_AVX, 0, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF)
 
-BDESC (OPTION_MASK_ISA_AVX, 0, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI)
-BDESC (OPTION_MASK_ISA_AVX, 0, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI)
-BDESC (OPTION_MASK_ISA_AVX, 0, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI)
-BDESC (OPTION_MASK_ISA_AVX, 0, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI)
 BDESC (OPTION_MASK_ISA_AVX, 0, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF)
 BDESC (OPTION_MASK_ISA_AVX, 0, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF)
 BDESC (OPTION_MASK_ISA_AVX, 0, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF)
@@ -198,10 +194,6 @@ BDESC (OPTION_MASK_ISA_AVX, 0, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_mask
 
 /* AVX2 */
 BDESC (OPTION_MASK_ISA_AVX2, 0, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI)
-BDESC (OPTION_MASK_ISA_AVX2, 0, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI)
-BDESC (OPTION_MASK_ISA_AVX2, 0, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI)
-BDESC (OPTION_MASK_ISA_AVX2, 0, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI)
-BDESC (OPTION_MASK_ISA_AVX2, 0, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI)
 BDESC (OPTION_MASK_ISA_AVX2, 0, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI)
 BDESC (OPTION_MASK_ISA_AVX2, 0, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI)
 BDESC (OPTION_MASK_ISA_AVX2, 0, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI)
diff --git a/gcc/config/i386/i386-builtins.c b/gcc/config/i386/i386-builtins.c
index 128bd39816c..2ffcbe5cd3e 100644
--- a/gcc/config/i386/i386-builtins.c
+++ b/gcc/config/i386/i386-builtins.c
@@ -667,7 +667,26 @@ ix86_init_mmx_sse_builtins (void)
 	       "__builtin_ia32_rdrand64_step", INT_FTYPE_PULONGLONG,
 	       IX86_BUILTIN_RDRAND64_STEP);
 
+  /* AVX */
+  def_builtin_pure (OPTION_MASK_ISA_AVX, 0, "__builtin_ia32_maskloadpd",
+		    V2DF_FTYPE_PCV2DF_V2DI, IX86_BUILTIN_MASKLOADPD);
+  def_builtin_pure (OPTION_MASK_ISA_AVX, 0, "__builtin_ia32_maskloadps",
+		    V4SF_FTYPE_PCV4SF_V4SI, IX86_BUILTIN_MASKLOADPS);
+  def_builtin_pure (OPTION_MASK_ISA_AVX, 0, "__builtin_ia32_maskloadpd256",
+		    V4DF_FTYPE_PCV4DF_V4DI, IX86_BUILTIN_MASKLOADPD256);
+  def_builtin_pure (OPTION_MASK_ISA_AVX, 0, "__builtin_ia32_maskloadps256",
+		    V8SF_FTYPE_PCV8SF_V8SI, IX86_BUILTIN_MASKLOADPS256);
+
   /* AVX2 */
+  def_builtin_pure (OPTION_MASK_ISA_AVX2, 0, "__builtin_ia32_maskloadd",
+		    V4SI_FTYPE_PCV4SI_V4SI, IX86_BUILTIN_MASKLOADD);
+  def_builtin_pure (OPTION_MASK_ISA_AVX2, 0, "__builtin_ia32_maskloadq",
+		    V2DI_FTYPE_PCV2DI_V2DI, IX86_BUILTIN_MASKLOADQ);
+  def_builtin_pure (OPTION_MASK_ISA_AVX2, 0, "__builtin_ia32_maskloadd256",
+		    V8SI_FTYPE_PCV8SI_V8SI, IX86_BUILTIN_MASKLOADD256);
+  def_builtin_pure (OPTION_MASK_ISA_AVX2, 0, "__builtin_ia32_maskloadq256",
+		    V4DI_FTYPE_PCV4DI_V4DI, IX86_BUILTIN_MASKLOADQ256);
+
   def_builtin_pure (OPTION_MASK_ISA_AVX2, 0, "__builtin_ia32_gathersiv2df",
 		    V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
 		    IX86_BUILTIN_GATHERSIV2DF);
diff --git a/gcc/config/i386/i386-builtins.h b/gcc/config/i386/i386-builtins.h
index 0641808c7a7..6a5e249e382 100644
--- a/gcc/config/i386/i386-builtins.h
+++ b/gcc/config/i386/i386-builtins.h
@@ -60,6 +60,14 @@ enum ix86_builtins
   IX86_BUILTIN_VEC_SET_V8HI,
   IX86_BUILTIN_VEC_SET_V4HI,
   IX86_BUILTIN_VEC_SET_V16QI,
+  IX86_BUILTIN_MASKLOADPD,
+  IX86_BUILTIN_MASKLOADPS,
+  IX86_BUILTIN_MASKLOADPD256,
+  IX86_BUILTIN_MASKLOADPS256,
+  IX86_BUILTIN_MASKLOADD,
+  IX86_BUILTIN_MASKLOADQ,
+  IX86_BUILTIN_MASKLOADD256,
+  IX86_BUILTIN_MASKLOADQ256,
   IX86_BUILTIN_GATHERSIV2DF,
   IX86_BUILTIN_GATHERSIV4DF,
   IX86_BUILTIN_GATHERDIV2DF,
-- 
2.26.2

^ permalink raw reply	[flat|nested] 8+ messages in thread

end of thread, other threads:[~2021-04-29 14:48 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-04-28 11:02 [PATCH] target/100312 - make x86 masked load builtins pure Richard Biener
2021-04-28 11:23 ` Uros Bizjak
2021-04-28 11:46   ` Richard Biener
2021-04-28 12:11     ` Uros Bizjak
2021-04-28 13:32       ` Richard Biener
2021-04-28 15:07         ` Uros Bizjak
2021-04-29  7:25           ` Richard Biener
2021-04-29 14:48             ` Uros Bizjak

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