From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qk1-x72c.google.com (mail-qk1-x72c.google.com [IPv6:2607:f8b0:4864:20::72c]) by sourceware.org (Postfix) with ESMTPS id AB723385701B for ; Fri, 16 Jun 2023 07:37:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org AB723385701B Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-qk1-x72c.google.com with SMTP id af79cd13be357-75d461fde66so46400785a.1 for ; Fri, 16 Jun 2023 00:37:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686901052; x=1689493052; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=uLT8ogZO7VqclxbXdFD4ZxGZrQ7rnbLfl+d9Bl2E39w=; b=ROudtdtWPFzJGElloX/Z5sKHUTQLuNTU0ackIqkAd6xR8acIugKpNkI82G6lemd/yh lo2/M8WSYkNX2czfZLDv+2APBn+afyS5Ysh5DhoD7zn7rKqI8984kl4iSZ05BkxaRvbv Zqt8xQHtKI8VfM8z7XZYYQvWvmwy35ABihcnZjzFIkUNcEVpU202o23xY1VQtQmBbJjc djYyhJICuZmVeTr34owK+yL3YX4DILOCEoaEFt/fbCjUIukjTHsd3ly/QJT8GFQT0Da2 iMTmsmraN6h44RRpmedH4ejBN220+SEdcAPn9ZXfEgMJ3E6Qqfe15FTz5+Dd+D+C1UdL ewhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686901052; x=1689493052; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uLT8ogZO7VqclxbXdFD4ZxGZrQ7rnbLfl+d9Bl2E39w=; b=bbr1CtJCvaw8+KrPBhNyoLmc2pfKVhV5vtW4eH2GlPXyPOvYVNL1vY9+EdGKL/Tn8o nHhdiyZL9/jeI0h7f24WebIoJK5NRNQIC7CjZPOcdlJFJrwjCSES18MAU+eiP+9KKYzk OiGfn70PbOqwLnAlleqXJ7kGaZbUNtT+OwXScpZI9DcEeq8itJu4Cog3mf2+y8083j4O xFpawhqLHnZcAVFzP0wfO7GipJ65ZqLJ6NE8u0Q/qoe1mw+AX8PQE9i4fK0UuD+uZ/iV wP/UfNhri22vBdmK9udI88gc/k3UkQ8t4712us38TNt+BIWUS8FPvQRTMbvvLTLA3miv se+Q== X-Gm-Message-State: AC+VfDxpB2/svjgtNb4lfdGsxC+dtTyhEfyJe77PvAMDPRoOhRZqYJWV Jb70WBVOBzneflllsyDfKVexIv6zJ/XOf6YmDfXlcxNe X-Google-Smtp-Source: ACHHUZ60Plj6Xidl1NdOSOfzaoXzik8nWNHs00mrJFtg34giSV/UySAN0Z/vBPmfwx4Hj3EXglVoxDcJIzAc2i2Ts1o= X-Received: by 2002:ad4:5be4:0:b0:625:b72a:142e with SMTP id k4-20020ad45be4000000b00625b72a142emr1530749qvc.12.1686901052306; Fri, 16 Jun 2023 00:37:32 -0700 (PDT) MIME-Version: 1.0 References: <20230616020958.1413585-1-hongtao.liu@intel.com> <20230616020958.1413585-2-hongtao.liu@intel.com> In-Reply-To: <20230616020958.1413585-2-hongtao.liu@intel.com> From: Uros Bizjak Date: Fri, 16 Jun 2023 09:37:25 +0200 Message-ID: Subject: Re: [PATCH 2/2] Refined 256/512-bit vpacksswb/vpackssdw patterns. To: liuhongt Cc: gcc-patches@gcc.gnu.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Fri, Jun 16, 2023 at 4:12=E2=80=AFAM liuhongt wr= ote: > > The packing in vpacksswb/vpackssdw is not a simple concat, it's an > interweave from src1 and src2 for every 128 bit(or 64-bit for the > ss_truncate result). > > .i.e. > > dst[192-255] =3D ss_truncate (src2[128-255]) > dst[128-191] =3D ss_truncate (src1[128-255]) > dst[64-127] =3D ss_truncate (src2[0-127]) > dst[0-63] =3D ss_truncate (src1[0-127] > > The patch refined those patterns with an extra vec_select for the > interweave. > > The patch will fix below testcase which failed after > g:921b841350c4fc298d09f6c5674663e0f4208610 added constant-folding for SS_= TRUNCATE > FAIL: gcc.target/i386/avx2-vpackssdw-2.c execution test. > > Bootstrapped and regtested on x86_64-pc-linux-gnu. > Ok for trunk? > > gcc/ChangeLog: > > PR target/110235 > * config/i386/sse.md (_packsswb): Split > to below 3 new define_insns. > (sse2_packsswb): New define_insn. > (avx2_packsswb): Ditto. > (avx512bw_packsswb): Ditto. > (_packssdw): Split to below 3 new define_in= sns. > (sse2_packssdw): New define_insn. > (avx2_packssdw): Ditto. > (avx512bw_packssdw): Ditto. > > gcc/testsuite/ChangeLog: > > * gcc.target/i386/avx512bw-vpackssdw-3.c: New test. > * gcc.target/i386/avx512bw-vpacksswb-3.c: New test. Please proofread and fix ChangeLog entry, in the same way as your previous patch. Otherwise LGTM. Thanks, Uros. > --- > gcc/config/i386/sse.md | 165 ++++++++++++++++-- > .../gcc.target/i386/avx512bw-vpackssdw-3.c | 55 ++++++ > .../gcc.target/i386/avx512bw-vpacksswb-3.c | 50 ++++++ > 3 files changed, 252 insertions(+), 18 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/i386/avx512bw-vpackssdw-3.c > create mode 100644 gcc/testsuite/gcc.target/i386/avx512bw-vpacksswb-3.c > > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md > index 83e3f534fd2..cc4e4620257 100644 > --- a/gcc/config/i386/sse.md > +++ b/gcc/config/i386/sse.md > @@ -17762,14 +17762,14 @@ (define_expand "vec_pack_sbool_trunc_qi" > DONE; > }) > > -(define_insn "_packsswb" > - [(set (match_operand:VI1_AVX512 0 "register_operand" "=3Dx,") > - (vec_concat:VI1_AVX512 > - (ss_truncate: > - (match_operand: 1 "register_operand" "0,= ")) > - (ss_truncate: > - (match_operand: 2 "vector_operand" "xBm,= m"))))] > - "TARGET_SSE2 && && " > +(define_insn "sse2_packsswb" > + [(set (match_operand:V16QI 0 "register_operand" "=3Dx,Yw") > + (vec_concat:V16QI > + (ss_truncate:V8QI > + (match_operand:V8HI 1 "register_operand" "0,Yw")) > + (ss_truncate:V8QI > + (match_operand:V8HI 2 "vector_operand" "xBm,Ywm"))))] > + "TARGET_SSE2 && && = " > "@ > packsswb\t{%2, %0|%0, %2} > vpacksswb\t{%2, %1, %0|%0, %1, %2}" > @@ -17777,16 +17777,93 @@ (define_insn "_packsswb" > (set_attr "type" "sselog") > (set_attr "prefix_data16" "1,*") > (set_attr "prefix" "orig,") > - (set_attr "mode" "")]) > + (set_attr "mode" "TI")]) > > -(define_insn "_packssdw" > - [(set (match_operand:VI2_AVX2 0 "register_operand" "=3Dx,") > - (vec_concat:VI2_AVX2 > - (ss_truncate: > - (match_operand: 1 "register_operand" "0,= ")) > - (ss_truncate: > - (match_operand: 2 "vector_operand" "xBm,= m"))))] > - "TARGET_SSE2 && && " > +(define_insn "avx2_packsswb" > + [(set (match_operand:V32QI 0 "register_operand" "=3DYw") > + (vec_select:V32QI > + (vec_concat:V32QI > + (ss_truncate:V16QI > + (match_operand:V16HI 1 "register_operand" "Yw")) > + (ss_truncate:V16QI > + (match_operand:V16HI 2 "vector_operand" "Ywm"))) > + (parallel [(const_int 0) (const_int 1) > + (const_int 2) (const_int 3) > + (const_int 4) (const_int 5) > + (const_int 6) (const_int 7) > + (const_int 16) (const_int 17) > + (const_int 18) (const_int 19) > + (const_int 20) (const_int 21) > + (const_int 22) (const_int 23) > + (const_int 8) (const_int 9) > + (const_int 10) (const_int 11) > + (const_int 12) (const_int 13) > + (const_int 14) (const_int 15) > + (const_int 24) (const_int 25) > + (const_int 26) (const_int 27) > + (const_int 28) (const_int 29) > + (const_int 30) (const_int 31)])))] > + "TARGET_AVX2 && && = " > + "vpacksswb\t{%2, %1, %0|%0, %1, %2}" > + [(set_attr "type" "sselog") > + (set_attr "prefix" "") > + (set_attr "mode" "OI")]) > + > +(define_insn "avx512bw_packsswb" > + [(set (match_operand:V64QI 0 "register_operand" "=3Dv") > + (vec_select:V64QI > + (vec_concat:V64QI > + (ss_truncate:V32QI > + (match_operand:V32HI 1 "register_operand" "v")) > + (ss_truncate:V32QI > + (match_operand:V32HI 2 "vector_operand" "vm"))) > + (parallel [(const_int 0) (const_int 1) > + (const_int 2) (const_int 3) > + (const_int 4) (const_int 5) > + (const_int 6) (const_int 7) > + (const_int 32) (const_int 33) > + (const_int 34) (const_int 35) > + (const_int 36) (const_int 37) > + (const_int 38) (const_int 39) > + (const_int 8) (const_int 9) > + (const_int 10) (const_int 11) > + (const_int 12) (const_int 13) > + (const_int 14) (const_int 15) > + (const_int 40) (const_int 41) > + (const_int 42) (const_int 43) > + (const_int 44) (const_int 45) > + (const_int 46) (const_int 47) > + (const_int 16) (const_int 17) > + (const_int 18) (const_int 19) > + (const_int 20) (const_int 21) > + (const_int 22) (const_int 23) > + (const_int 48) (const_int 49) > + (const_int 50) (const_int 51) > + (const_int 52) (const_int 53) > + (const_int 54) (const_int 55) > + (const_int 24) (const_int 25) > + (const_int 26) (const_int 27) > + (const_int 28) (const_int 29) > + (const_int 30) (const_int 31) > + (const_int 56) (const_int 57) > + (const_int 58) (const_int 59) > + (const_int 60) (const_int 61) > + (const_int 62) (const_int 63)])))] > + > + "TARGET_AVX512BW" > + "vpacksswb\t{%2, %1, %0|%0, %1, %2}" > + [(set_attr "type" "sselog") > + (set_attr "prefix" "") > + (set_attr "mode" "XI")]) > + > +(define_insn "sse2_packssdw" > + [(set (match_operand:V8HI 0 "register_operand" "=3Dx,Yw") > + (vec_concat:V8HI > + (ss_truncate:V4HI > + (match_operand:V4SI 1 "register_operand" "0,Yw")) > + (ss_truncate:V4HI > + (match_operand:V4SI 2 "vector_operand" "xBm,Ywm"))))] > + "TARGET_SSE2 && && = " > "@ > packssdw\t{%2, %0|%0, %2} > vpackssdw\t{%2, %1, %0|%0, %1, %2}" > @@ -17794,7 +17871,59 @@ (define_insn "_packssdw" > (set_attr "type" "sselog") > (set_attr "prefix_data16" "1,*") > (set_attr "prefix" "orig,") > - (set_attr "mode" "")]) > + (set_attr "mode" "TI")]) > + > +(define_insn "avx2_packssdw" > + [(set (match_operand:V16HI 0 "register_operand" "=3DYw") > + (vec_select:V16HI > + (vec_concat:V16HI > + (ss_truncate:V8HI > + (match_operand:V8SI 1 "register_operand" "Yw")) > + (ss_truncate:V8HI > + (match_operand:V8SI 2 "vector_operand" "Ywm"))) > + (parallel [(const_int 0) (const_int 1) > + (const_int 2) (const_int 3) > + (const_int 8) (const_int 9) > + (const_int 10) (const_int 11) > + (const_int 4) (const_int 5) > + (const_int 6) (const_int 7) > + (const_int 12) (const_int 13) > + (const_int 14) (const_int 15)])))] > + "TARGET_AVX2 && && = " > + "vpackssdw\t{%2, %1, %0|%0, %1, %2}" > + [(set_attr "type" "sselog") > + (set_attr "prefix" "") > + (set_attr "mode" "OI")]) > + > +(define_insn "avx512bw_packssdw" > + [(set (match_operand:V32HI 0 "register_operand" "=3Dv") > + (vec_select:V32HI > + (vec_concat:V32HI > + (ss_truncate:V16HI > + (match_operand:V16SI 1 "register_operand" "v")) > + (ss_truncate:V16HI > + (match_operand:V16SI 2 "vector_operand" "vm"))) > + (parallel [(const_int 0) (const_int 1) > + (const_int 2) (const_int 3) > + (const_int 16) (const_int 17) > + (const_int 18) (const_int 19) > + (const_int 4) (const_int 5) > + (const_int 6) (const_int 7) > + (const_int 20) (const_int 21) > + (const_int 22) (const_int 23) > + (const_int 8) (const_int 9) > + (const_int 10) (const_int 11) > + (const_int 24) (const_int 25) > + (const_int 26) (const_int 27) > + (const_int 12) (const_int 13) > + (const_int 14) (const_int 15) > + (const_int 28) (const_int 29) > + (const_int 30) (const_int 31)])))] > + "TARGET_AVX512BW" > + "vpackssdw\t{%2, %1, %0|%0, %1, %2}" > + [(set_attr "type" "sselog") > + (set_attr "prefix" "") > + (set_attr "mode" "XI")]) > > ;; This is different from rtl unsigned saturation, the instruction does > ;; unsigned saturation for signed value. > diff --git a/gcc/testsuite/gcc.target/i386/avx512bw-vpackssdw-3.c b/gcc/t= estsuite/gcc.target/i386/avx512bw-vpackssdw-3.c > new file mode 100644 > index 00000000000..ae839e8d2c6 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/avx512bw-vpackssdw-3.c > @@ -0,0 +1,55 @@ > +/* { dg-do run } */ > +/* { dg-options "-O2 -mavx512bw" } */ > +/* { dg-require-effective-target avx512bw } */ > + > +#define AVX512BW > +#include "avx512f-helper.h" > + > +#define DST_SIZE (AVX512F_LEN / 16) > +#define SRC_SIZE (AVX512F_LEN / 32) > + > +#include "limits.h" > + > +#include "avx512f-mask-type.h" > + > +static short > +int_to_short (int iVal) > +{ > + short sVal; > + > + if (iVal < -32768) > + sVal =3D -32768; > + else if (iVal > 32767) > + sVal =3D 32767; > + else > + sVal =3D iVal; > + > + return sVal; > +} > + > +void > +TEST (void) > +{ > + union512i_d s1, s2; > + union512i_w res1; > + short dst_ref[32]; > + int i; > + > + s1.x =3D _mm512_set_epi32 (1, 2, 3, 4, 65000, 20, 30, 90, 88, 44, 33, = 22, 11, 98, 76, -65000); > + s2.x =3D _mm512_set_epi32 (80, 40, 31, 21, 10, 99, 74, -65000, 2, 3, 4= , 5, 65010, 21, 31, 91); > + res1.x =3D _mm512_packs_epi32 (s1.x, s2.x); > + for (int i =3D 0; i !=3D 4; i++) > + { > + dst_ref[i] =3D int_to_short (s1.a[i]); > + dst_ref[i + 4] =3D int_to_short (s2.a[i]); > + dst_ref[i + 8] =3D int_to_short (s1.a[i + 4]); > + dst_ref[i + 12] =3D int_to_short (s2.a[i + 4]); > + dst_ref[i + 16] =3D int_to_short (s1.a[i + 8]); > + dst_ref[i + 20] =3D int_to_short (s2.a[i + 8]); > + dst_ref[i + 24] =3D int_to_short (s1.a[i + 12]); > + dst_ref[i + 28] =3D int_to_short (s2.a[i + 12]); > + } > + > + if (check_union512i_w (res1, dst_ref)) > + abort (); > +} > diff --git a/gcc/testsuite/gcc.target/i386/avx512bw-vpacksswb-3.c b/gcc/t= estsuite/gcc.target/i386/avx512bw-vpacksswb-3.c > new file mode 100644 > index 00000000000..056c735ae0e > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/avx512bw-vpacksswb-3.c > @@ -0,0 +1,50 @@ > +/* { dg-do run } */ > +/* { dg-options "-O2 -mavx512bw" } */ > +/* { dg-require-effective-target avx512bw } */ > + > +#define AVX512BW > +#include "avx512f-helper.h" > + > +static char > +short_to_byte (short iVal) > +{ > + short sVal; > + > + if (iVal < -128) > + sVal =3D -128; > + else if (iVal > 127) > + sVal =3D 127; > + else > + sVal =3D iVal; > + > + return sVal; > +} > + > +void > +TEST (void) > +{ > + union512i_w s1, s2; > + union512i_b res1; > + char dst_ref[64]; > + int i; > + > + s1.x =3D _mm512_set_epi16 (1, 2, 3, 4, 650, 20, 30, 90, 88, 44, 33, 22= , 11, 98, 76, -650, > + 128, 230, -112, -128, -3, -4, -7, 9, 10, 11, 1= 2, 13, -223, 10, 8, 11); > + s2.x =3D _mm512_set_epi16 (80, 40, 31, 21, 10, 99, 74, -650, 2, 3, 4, = 5, 650, 21, 31, 91, > + 280, -140, 310, 20, 9, 98, 73, -651, 3, 4, 5, = 6, 651, 22, 32, 92); > + res1.x =3D _mm512_packs_epi16 (s1.x, s2.x); > + for (int i =3D 0; i !=3D 8; i++) > + { > + dst_ref[i] =3D short_to_byte (s1.a[i]); > + dst_ref[i + 8] =3D short_to_byte (s2.a[i]); > + dst_ref[i + 16] =3D short_to_byte (s1.a[i + 8]); > + dst_ref[i + 24] =3D short_to_byte (s2.a[i + 8]); > + dst_ref[i + 32] =3D short_to_byte (s1.a[i + 16]); > + dst_ref[i + 40] =3D short_to_byte (s2.a[i + 16]); > + dst_ref[i + 48] =3D short_to_byte (s1.a[i + 24]); > + dst_ref[i + 56] =3D short_to_byte (s2.a[i + 24]); > + } > + > + if (check_union512i_b (res1, dst_ref)) > + abort (); > +} > -- > 2.39.1.388.g2fc9e9ca3c >