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* [PATCH] Support 64bit fma/fms/fnma/fnms under avx512vl.
@ 2021-09-22  5:09 liuhongt
  2021-09-22  6:09 ` Uros Bizjak
  0 siblings, 1 reply; 2+ messages in thread
From: liuhongt @ 2021-09-22  5:09 UTC (permalink / raw)
  To: gcc-patches

Hi:
  fma/fms/fnma/fnmsv2sf4 are defined only under (TARGET_FMA || TARGET_FMA4).
The patch extend the expanders to TARGET_AVX512VL.

  Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
  Ok for trunk?

gcc/ChangeLog:

	* config/i386/mmx.md (fmav2sf4): Extend to AVX512 fma.
	(fmsv2sf4): Ditto.
	(fnmav2sf4): Ditto.
	(fnmsv2sf4): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/avx512vl-pr95046.c: New test.
---
 gcc/config/i386/i386.md                       |  4 +++-
 gcc/config/i386/mmx.md                        | 20 +++++++++++--------
 .../gcc.target/i386/avx512vl-pr95046.c        | 10 ++++++++++
 3 files changed, 25 insertions(+), 9 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-pr95046.c

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 188f431510a..c41fdd516c5 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -832,7 +832,7 @@ (define_attr "isa" "base,x64,nox64,x64_sse2,x64_sse4,x64_sse4_noavx,
 		    x64_avx,x64_avx512bw,x64_avx512dq,
 		    sse_noavx,sse2,sse2_noavx,sse3,sse3_noavx,sse4,sse4_noavx,
 		    avx,noavx,avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,noavx512f,
-		    avx512bw,noavx512bw,avx512dq,noavx512dq,
+		    avx512bw,noavx512bw,avx512dq,noavx512dq,fma_or_avx512vl,
 		    avx512vl,noavx512vl,avxvnni,avx512vnnivl,avx512fp16"
   (const_string "base"))
 
@@ -874,6 +874,8 @@ (define_attr "enabled" ""
 	 (eq_attr "isa" "bmi2") (symbol_ref "TARGET_BMI2")
 	 (eq_attr "isa" "fma4") (symbol_ref "TARGET_FMA4")
 	 (eq_attr "isa" "fma") (symbol_ref "TARGET_FMA")
+	 (eq_attr "isa" "fma_or_avx512vl")
+	   (symbol_ref "TARGET_FMA || TARGET_AVX512VL")
 	 (eq_attr "isa" "avx512f") (symbol_ref "TARGET_AVX512F")
 	 (eq_attr "isa" "noavx512f") (symbol_ref "!TARGET_AVX512F")
 	 (eq_attr "isa" "avx512bw") (symbol_ref "TARGET_AVX512BW")
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 2d3b63f0834..b0093778fc6 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -1019,12 +1019,13 @@ (define_insn "fmav2sf4"
 	  (match_operand:V2SF 1 "register_operand" "%0,v,x")
 	  (match_operand:V2SF 2 "register_operand" "v,v,x")
 	  (match_operand:V2SF 3 "register_operand" "v,0,x")))]
-  "(TARGET_FMA || TARGET_FMA4) && TARGET_MMX_WITH_SSE"
+  "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL)
+   && TARGET_MMX_WITH_SSE"
   "@
    vfmadd132ps\t{%2, %3, %0|%0, %3, %2}
    vfmadd231ps\t{%2, %1, %0|%0, %1, %2}
    vfmaddps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
-  [(set_attr "isa" "fma,fma,fma4")
+  [(set_attr "isa" "fma_or_avx512vl,fma_or_avx512vl,fma4")
    (set_attr "type" "ssemuladd")
    (set_attr "mode" "V4SF")])
 
@@ -1035,12 +1036,13 @@ (define_insn "fmsv2sf4"
 	  (match_operand:V2SF   2 "register_operand" "v,v,x")
 	  (neg:V2SF
 	    (match_operand:V2SF 3 "register_operand" "v,0,x"))))]
-  "(TARGET_FMA || TARGET_FMA4) && TARGET_MMX_WITH_SSE"
+  "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL)
+   && TARGET_MMX_WITH_SSE"
   "@
    vfmsub132ps\t{%2, %3, %0|%0, %3, %2}
    vfmsub231ps\t{%2, %1, %0|%0, %1, %2}
    vfmsubps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
-  [(set_attr "isa" "fma,fma,fma4")
+  [(set_attr "isa" "fma_or_avx512vl,fma_or_avx512vl,fma4")
    (set_attr "type" "ssemuladd")
    (set_attr "mode" "V4SF")])
 
@@ -1051,12 +1053,13 @@ (define_insn "fnmav2sf4"
 	    (match_operand:V2SF 1 "register_operand" "%0,v,x"))
 	  (match_operand:V2SF   2 "register_operand" "v,v,x")
 	  (match_operand:V2SF   3 "register_operand" "v,0,x")))]
-  "(TARGET_FMA || TARGET_FMA4) && TARGET_MMX_WITH_SSE"
+  "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL)
+   && TARGET_MMX_WITH_SSE"
   "@
    vfnmadd132ps\t{%2, %3, %0|%0, %3, %2}
    vfnmadd231ps\t{%2, %1, %0|%0, %1, %2}
    vfnmaddps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
-  [(set_attr "isa" "fma,fma,fma4")
+  [(set_attr "isa" "fma_or_avx512vl,fma_or_avx512vl,fma4")
    (set_attr "type" "ssemuladd")
    (set_attr "mode" "V4SF")])
 
@@ -1068,12 +1071,13 @@ (define_insn "fnmsv2sf4"
 	  (match_operand:V2SF   2 "register_operand" "v,v,x")
 	  (neg:V2SF
 	    (match_operand:V2SF 3 "register_operand" "v,0,x"))))]
-  "(TARGET_FMA || TARGET_FMA4) && TARGET_MMX_WITH_SSE"
+  "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL)
+   && TARGET_MMX_WITH_SSE"
   "@
    vfnmsub132ps\t{%2, %3, %0|%0, %3, %2}
    vfnmsub231ps\t{%2, %1, %0|%0, %1, %2}
    vfnmsubps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
-  [(set_attr "isa" "fma,fma,fma4")
+  [(set_attr "isa" "fma_or_avx512vl,fma_or_avx512vl,fma4")
    (set_attr "type" "ssemuladd")
    (set_attr "mode" "V4SF")])
 
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-pr95046.c b/gcc/testsuite/gcc.target/i386/avx512vl-pr95046.c
new file mode 100644
index 00000000000..02204d0e3c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-pr95046.c
@@ -0,0 +1,10 @@
+/* PR target/95046 */
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O3 -mavx512vl" } */
+
+#include "pr95046-3.c"
+
+/* { dg-final { scan-assembler "\tvfmadd\[123\]+ps" } } */
+/* { dg-final { scan-assembler "\tvfmsub\[123\]+ps" } } */
+/* { dg-final { scan-assembler "\tvfnmadd\[123\]+ps" } } */
+/* { dg-final { scan-assembler "\tvfnmsub\[123\]+ps" } } */
-- 
2.27.0


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2021-09-22  5:09 [PATCH] Support 64bit fma/fms/fnma/fnms under avx512vl liuhongt
2021-09-22  6:09 ` Uros Bizjak

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