* [PATCH, i386] Merge SSE and AVX ptest patterns.
@ 2015-08-04 11:59 Kirill Yukhin
2015-08-04 12:06 ` Uros Bizjak
0 siblings, 1 reply; 3+ messages in thread
From: Kirill Yukhin @ 2015-08-04 11:59 UTC (permalink / raw)
To: GCC Patches; +Cc: Uros Bizjak
Hello,
I've merged ptest insn patterns from AVX and SSE.
I've also extended mode iterator to allow any 128/256 bit mode
for the insn as it register-wide, which may help implementing
https://gcc.gnu.org/ml/gcc-patches/2015-05/msg02788.html
Bootstrapped and regtested.
If no objections, I'll commit it into main trunk tomorrow morning (Moscow time).
gcc/
* config/i386/i386.c (bdesc_args): Rename CODE_FOR_sse4_1_ptest into
CODE_FOR_sse4_1_ptestv2di and CODE_FOR_avx_vtestps256 into
CODE_FOR_avx_ptestv4di.
* config/i386/sse.md (define_mode_iterator V_AVX): New.
(define_mode_attr sse4_1): Extend to other 128/256-bit modes.
(define_insn "avx_ptest256"): Merge this ...
(define_insn "sse4_1_ptest"): And this ...
(define_insn "<sse4_1>_ptest<mode>"): Into this. Use V_AVX iterator.
--
Thanks, K
commit 64741d31c19d464a1ca4270b775a7b54c1253019
Author: Kirill Yukhin <kirill.yukhin@intel.com>
Date: Tue Aug 4 10:36:10 2015 +0300
Merge SSE 4.1 and AVX ptest patterns. Extend iterator for new one.
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 128c5af..f93a5ce 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -31734,9 +31734,9 @@ static const struct builtin_description bdesc_args[] =
{ OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
{ OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
- { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
- { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
- { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
+ { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptestv2di, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
+ { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptestv2di, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
+ { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptestv2di, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
/* SSE4.2 */
{ OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
@@ -31892,9 +31892,9 @@ static const struct builtin_description bdesc_args[] =
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
- { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
- { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
- { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
+ { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptestv4di, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
+ { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptestv4di, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
+ { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptestv4di, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 0970f0e..f9994e4 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -299,6 +299,12 @@
V8DI (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")])
;; All DImode vector integer modes
+(define_mode_iterator V_AVX
+ [V16QI V8HI V4SI V2DI V4SF V2DF
+ (V32QI "TARGET_AVX") (V16HI "TARGET_AVX")
+ (V8SI "TARGET_AVX") (V4DI "TARGET_AVX")
+ (V8SF "TARGET_AVX") (V4DF"TARGET_AVX")])
+
(define_mode_iterator VI8
[(V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX") V2DI])
@@ -566,7 +572,11 @@
(define_mode_attr sse4_1
[(V4SF "sse4_1") (V2DF "sse4_1")
(V8SF "avx") (V4DF "avx")
- (V8DF "avx512f")])
+ (V8DF "avx512f")
+ (V4DI "avx") (V2DI "sse4_1")
+ (V8SI "avx") (V4SI "sse4_1")
+ (V16QI "sse4_1") (V32QI "avx")
+ (V8HI "sse4_1") (V16HI "avx")])
(define_mode_attr avxsizesuffix
[(V64QI "512") (V32HI "512") (V16SI "512") (V8DI "512")
@@ -14640,30 +14650,24 @@
;; ptest is very similar to comiss and ucomiss when setting FLAGS_REG.
;; But it is not a really compare instruction.
-(define_insn "avx_ptest256"
- [(set (reg:CC FLAGS_REG)
- (unspec:CC [(match_operand:V4DI 0 "register_operand" "x")
- (match_operand:V4DI 1 "nonimmediate_operand" "xm")]
- UNSPEC_PTEST))]
- "TARGET_AVX"
- "vptest\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecomi")
- (set_attr "prefix_extra" "1")
- (set_attr "prefix" "vex")
- (set_attr "btver2_decode" "vector")
- (set_attr "mode" "OI")])
-
-(define_insn "sse4_1_ptest"
+(define_insn "<sse4_1>_ptest<mode>"
[(set (reg:CC FLAGS_REG)
- (unspec:CC [(match_operand:V2DI 0 "register_operand" "Yr,*x")
- (match_operand:V2DI 1 "nonimmediate_operand" "Yrm,*xm")]
+ (unspec:CC [(match_operand:V_AVX 0 "register_operand" "Yr, *x, x")
+ (match_operand:V_AVX 1 "nonimmediate_operand" "Yrm, *xm, xm")]
UNSPEC_PTEST))]
"TARGET_SSE4_1"
"%vptest\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecomi")
+ [(set_attr "isa" "*,*,avx")
+ (set_attr "type" "ssecomi")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_vex")
- (set_attr "mode" "TI")])
+ (set (attr "btver2_decode")
+ (if_then_else
+ (and (eq_attr "alternative" "2")
+ (match_test "<sseinsnmode>mode==OImode"))
+ (const_string "vector")
+ (const_string "*")))
+ (set_attr "mode" "<sseinsnmode>")])
(define_insn "<sse4_1>_round<ssemodesuffix><avxsizesuffix>"
[(set (match_operand:VF_128_256 0 "register_operand" "=Yr,*x")
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH, i386] Merge SSE and AVX ptest patterns.
2015-08-04 11:59 [PATCH, i386] Merge SSE and AVX ptest patterns Kirill Yukhin
@ 2015-08-04 12:06 ` Uros Bizjak
2015-08-04 12:33 ` Kirill Yukhin
0 siblings, 1 reply; 3+ messages in thread
From: Uros Bizjak @ 2015-08-04 12:06 UTC (permalink / raw)
To: Kirill Yukhin; +Cc: GCC Patches
On Tue, Aug 4, 2015 at 1:58 PM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:
> Hello,
> I've merged ptest insn patterns from AVX and SSE.
> I've also extended mode iterator to allow any 128/256 bit mode
> for the insn as it register-wide, which may help implementing
> https://gcc.gnu.org/ml/gcc-patches/2015-05/msg02788.html
>
>
> Bootstrapped and regtested.
>
> If no objections, I'll commit it into main trunk tomorrow morning (Moscow time).
>
> gcc/
> * config/i386/i386.c (bdesc_args): Rename CODE_FOR_sse4_1_ptest into
> CODE_FOR_sse4_1_ptestv2di and CODE_FOR_avx_vtestps256 into
> CODE_FOR_avx_ptestv4di.
> * config/i386/sse.md (define_mode_iterator V_AVX): New.
> (define_mode_attr sse4_1): Extend to other 128/256-bit modes.
> (define_insn "avx_ptest256"): Merge this ...
> (define_insn "sse4_1_ptest"): And this ...
> (define_insn "<sse4_1>_ptest<mode>"): Into this. Use V_AVX iterator.
>
> + (set (attr "btver2_decode")
> + (if_then_else
> + (and (eq_attr "alternative" "2")
> + (match_test "<sseinsnmode>mode==OImode"))
> + (const_string "vector")
> + (const_string "*")))
"vector" does not depend on alternative, but only on
<sseinsnsmode>mode. So the and above should be removed.
Uros.
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH, i386] Merge SSE and AVX ptest patterns.
2015-08-04 12:06 ` Uros Bizjak
@ 2015-08-04 12:33 ` Kirill Yukhin
0 siblings, 0 replies; 3+ messages in thread
From: Kirill Yukhin @ 2015-08-04 12:33 UTC (permalink / raw)
To: Uros Bizjak; +Cc: GCC Patches
On 04 Aug 14:06, Uros Bizjak wrote:
> On Tue, Aug 4, 2015 at 1:58 PM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:
> > + (set (attr "btver2_decode")
> > + (if_then_else
> > + (and (eq_attr "alternative" "2")
> > + (match_test "<sseinsnmode>mode==OImode"))
> > + (const_string "vector")
> > + (const_string "*")))
>
> "vector" does not depend on alternative, but only on
> <sseinsnsmode>mode. So the and above should be removed.
Thanks, fixed!
> Uros.
commit 20df38ce6fed082155b9860b0a1c5511894fdd84
Author: Kirill Yukhin <kirill.yukhin@intel.com>
Date: Tue Aug 4 10:36:10 2015 +0300
Merge SSE 4.1 and AVX ptest patterns. Extend iterator for new one.
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 128c5af..f93a5ce 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -31734,9 +31734,9 @@ static const struct builtin_description bdesc_args[] =
{ OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
{ OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
- { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
- { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
- { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
+ { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptestv2di, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
+ { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptestv2di, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
+ { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptestv2di, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
/* SSE4.2 */
{ OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
@@ -31892,9 +31892,9 @@ static const struct builtin_description bdesc_args[] =
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
- { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
- { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
- { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
+ { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptestv4di, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
+ { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptestv4di, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
+ { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptestv4di, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 0970f0e..0ffc27d 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -299,6 +299,12 @@
V8DI (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")])
;; All DImode vector integer modes
+(define_mode_iterator V_AVX
+ [V16QI V8HI V4SI V2DI V4SF V2DF
+ (V32QI "TARGET_AVX") (V16HI "TARGET_AVX")
+ (V8SI "TARGET_AVX") (V4DI "TARGET_AVX")
+ (V8SF "TARGET_AVX") (V4DF"TARGET_AVX")])
+
(define_mode_iterator VI8
[(V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX") V2DI])
@@ -566,7 +572,11 @@
(define_mode_attr sse4_1
[(V4SF "sse4_1") (V2DF "sse4_1")
(V8SF "avx") (V4DF "avx")
- (V8DF "avx512f")])
+ (V8DF "avx512f")
+ (V4DI "avx") (V2DI "sse4_1")
+ (V8SI "avx") (V4SI "sse4_1")
+ (V16QI "sse4_1") (V32QI "avx")
+ (V8HI "sse4_1") (V16HI "avx")])
(define_mode_attr avxsizesuffix
[(V64QI "512") (V32HI "512") (V16SI "512") (V8DI "512")
@@ -14640,30 +14650,23 @@
;; ptest is very similar to comiss and ucomiss when setting FLAGS_REG.
;; But it is not a really compare instruction.
-(define_insn "avx_ptest256"
- [(set (reg:CC FLAGS_REG)
- (unspec:CC [(match_operand:V4DI 0 "register_operand" "x")
- (match_operand:V4DI 1 "nonimmediate_operand" "xm")]
- UNSPEC_PTEST))]
- "TARGET_AVX"
- "vptest\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecomi")
- (set_attr "prefix_extra" "1")
- (set_attr "prefix" "vex")
- (set_attr "btver2_decode" "vector")
- (set_attr "mode" "OI")])
-
-(define_insn "sse4_1_ptest"
+(define_insn "<sse4_1>_ptest<mode>"
[(set (reg:CC FLAGS_REG)
- (unspec:CC [(match_operand:V2DI 0 "register_operand" "Yr,*x")
- (match_operand:V2DI 1 "nonimmediate_operand" "Yrm,*xm")]
+ (unspec:CC [(match_operand:V_AVX 0 "register_operand" "Yr, *x, x")
+ (match_operand:V_AVX 1 "nonimmediate_operand" "Yrm, *xm, xm")]
UNSPEC_PTEST))]
"TARGET_SSE4_1"
"%vptest\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecomi")
+ [(set_attr "isa" "*,*,avx")
+ (set_attr "type" "ssecomi")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_vex")
- (set_attr "mode" "TI")])
+ (set (attr "btver2_decode")
+ (if_then_else
+ (match_test "<sseinsnmode>mode==OImode")
+ (const_string "vector")
+ (const_string "*")))
+ (set_attr "mode" "<sseinsnmode>")])
(define_insn "<sse4_1>_round<ssemodesuffix><avxsizesuffix>"
[(set (match_operand:VF_128_256 0 "register_operand" "=Yr,*x")
^ permalink raw reply [flat|nested] 3+ messages in thread
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2015-08-04 11:59 [PATCH, i386] Merge SSE and AVX ptest patterns Kirill Yukhin
2015-08-04 12:06 ` Uros Bizjak
2015-08-04 12:33 ` Kirill Yukhin
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