Re: [PATCH] i386: Fix some -mavx512vl -mno-avx512bw bugs [PR99321]

[Uros Bizjak <ubizjak@gmail.com>]

On Sat, Mar 6, 2021 at 11:34 AM Jakub Jelinek <jakub@redhat.com> wrote:
>
> On Sat, Mar 06, 2021 at 11:19:15AM +0100, Uros Bizjak wrote:
> > > We already have Yw constraint which is equivalent to v for
> > > -mavx512bw -mavx512vl and to nothing otherwise, so for
> > > the instructions that need both we need to use xYw and
> > > v for modes that don't need that.
> >
> > Perhaps we should introduce another Y... constraint to return correct
> > SSE regset based on TARGET_... flags, instead of using compound xYw? I
> > think that introducing new constraint is the established approach we
> > should follow. The new mode_attr looks OK to me.
>
> One possibility would be to change the meaning of Yw, because it
> is an internal undocumented constraint and all uses in GCC currently use it
> as xYw:
> constraints.md:(define_register_constraint "Yw"
> mmx.md:  [(set (match_operand:V4HI 0 "register_operand" "=y,xYw")
> mmx.md:          (match_operand:V4HI 1 "register_mmxmem_operand" "ym,xYw")
> mmx.md:  [(set (match_operand:V4HI 0 "register_operand" "=y,xYw")
> mmx.md:     (match_operand:SI 1 "register_operand" "0,xYw"))))]
> Would that be ok?

Yes, this is an excellent idea.

Uros.

> If not, I'll add
> (define_register_constraint "Yl"
>  "TARGET_AVX512BW && TARGET_AVX512VL ? ALL_SSE_REGS : TARGET_SSE ? SSE_REGS : NO_REGS"
>  "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512BW with TARGET_AVX512VL target, otherwise any SSE register.")
>
>         Jakub
>