From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qk1-x734.google.com (mail-qk1-x734.google.com [IPv6:2607:f8b0:4864:20::734]) by sourceware.org (Postfix) with ESMTPS id ED170388C01C for ; Sat, 6 Mar 2021 12:39:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org ED170388C01C Received: by mail-qk1-x734.google.com with SMTP id a9so4756595qkn.13 for ; Sat, 06 Mar 2021 04:39:30 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=MEm94b4/57qzVQsTwLuRzlhKqI4hJ1EjgDUK6UyIi/A=; b=F1jOl0IjSGWSDwr3zCfyA7C9emilffNm+y+HAGAPk/v4ZIkhXiF85bzV4znsX6vJo7 P7QPr9LkTrJDhSnfoA3Y6dBMwjeTiZdICgUr5i/4Rytj0vdj0ixCEtLQ0g0FGDGaWl3n h/IdMRU7DUKMiHaqyt4A/7IHTIlOJrJde2G+x3aguZqTFp8gHX4UGbnxckQfVfTeQrCm cYwqAB3gk0R+Z79dMDMK613I8IbzZXmdIMWtclkgpFNLZCbocTVCfdWDgTIHLPnUJ+Ps EOerld8N6gEgs9c6Fhm4pqJ6P9EF4DptSzqTIx+Ep1E0XMzVMvxgAiRQL35W9hBghkxi Nu1Q== X-Gm-Message-State: AOAM530aYkIZCSNYom9mQJHTXldpOMGe4IwtHUVq12C5mtz3cBrvZqeM up/Icr1lCKpjpdWYIpbOYXqHSH8g5hJFo3PmmQo= X-Google-Smtp-Source: ABdhPJyAbKivHuNxlzU+dUFlQCZSBY7oA15oLZFGuOd17S0ri3elZEFcMBYUrmOPNBjUheSn6WsLH+UCLMHxg7OjdVU= X-Received: by 2002:a37:9c4a:: with SMTP id f71mr13218673qke.74.1615034370543; Sat, 06 Mar 2021 04:39:30 -0800 (PST) MIME-Version: 1.0 References: <20210305205058.GN745611@tucnak> <20210306103436.GP745611@tucnak> In-Reply-To: <20210306103436.GP745611@tucnak> From: Uros Bizjak Date: Sat, 6 Mar 2021 13:39:23 +0100 Message-ID: Subject: Re: [PATCH] i386: Fix some -mavx512vl -mno-avx512bw bugs [PR99321] To: Jakub Jelinek Cc: "H. J. Lu" , Jeff Law , Kirill Yukhin , "gcc-patches@gcc.gnu.org" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 06 Mar 2021 12:39:32 -0000 On Sat, Mar 6, 2021 at 11:34 AM Jakub Jelinek wrote: > > On Sat, Mar 06, 2021 at 11:19:15AM +0100, Uros Bizjak wrote: > > > We already have Yw constraint which is equivalent to v for > > > -mavx512bw -mavx512vl and to nothing otherwise, so for > > > the instructions that need both we need to use xYw and > > > v for modes that don't need that. > > > > Perhaps we should introduce another Y... constraint to return correct > > SSE regset based on TARGET_... flags, instead of using compound xYw? I > > think that introducing new constraint is the established approach we > > should follow. The new mode_attr looks OK to me. > > One possibility would be to change the meaning of Yw, because it > is an internal undocumented constraint and all uses in GCC currently use it > as xYw: > constraints.md:(define_register_constraint "Yw" > mmx.md: [(set (match_operand:V4HI 0 "register_operand" "=y,xYw") > mmx.md: (match_operand:V4HI 1 "register_mmxmem_operand" "ym,xYw") > mmx.md: [(set (match_operand:V4HI 0 "register_operand" "=y,xYw") > mmx.md: (match_operand:SI 1 "register_operand" "0,xYw"))))] > Would that be ok? Yes, this is an excellent idea. Uros. > If not, I'll add > (define_register_constraint "Yl" > "TARGET_AVX512BW && TARGET_AVX512VL ? ALL_SSE_REGS : TARGET_SSE ? SSE_REGS : NO_REGS" > "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512BW with TARGET_AVX512VL target, otherwise any SSE register.") > > Jakub >