From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 53478 invoked by alias); 14 Feb 2019 14:17:33 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 53459 invoked by uid 89); 14 Feb 2019 14:17:33 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00,FREEMAIL_FROM,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-it1-f193.google.com Received: from mail-it1-f193.google.com (HELO mail-it1-f193.google.com) (209.85.166.193) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 14 Feb 2019 14:17:31 +0000 Received: by mail-it1-f193.google.com with SMTP id y184so15324659itc.1 for ; Thu, 14 Feb 2019 06:17:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=kqj6jzqJjPGA9+BdJ5/05wCUBmB7+z+alYbSQhgMVfo=; b=Sunih4EYq+JDmZsfILqD5f3bSs65kUXOgZgqVS/lk5sxKXR+Dub4+RId34PE1RXB6i 5t6hU78CM2o4dpOh8m1d6AEFLXv/iItOCR+/TWX6Mdpto6M76Juq9DdYpmbkT4tvrWqM T/u0L87i7bwYUC3Rd5KbYrZ74sLtQxtr4a7TIJg+d5a+aV39N5n69YVsUf49/sRcgCZg lZlC8ABI4ILsquxPbtlx7CgA3Fhu2N9zPyHysfEIKVSH7JkZeFNkvjPFT2ZKPetIZz4i PUwa3M/xJv9IejDbiAuUQYv2ZRKyoKpbiVnO5g/F9GSzRMPqq5UQbPucmiasanpXRloC FczQ== MIME-Version: 1.0 References: <20190214123031.13301-1-hjl.tools@gmail.com> <20190214123031.13301-26-hjl.tools@gmail.com> In-Reply-To: <20190214123031.13301-26-hjl.tools@gmail.com> From: Uros Bizjak Date: Thu, 14 Feb 2019 14:17:00 -0000 Message-ID: Subject: Re: [PATCH 25/40] i386: Emulate MMX movntq with SSE2 movntidi To: "H.J. Lu" Cc: "gcc-patches@gcc.gnu.org" Content-Type: text/plain; charset="UTF-8" X-SW-Source: 2019-02/txt/msg01080.txt.bz2 On Thu, Feb 14, 2019 at 1:30 PM H.J. Lu wrote: > > Emulate MMX movntq with SSE2 movntidi. Only SSE register source operand > is allowed. There is no SSE register source operand. Probably "Only register source operand is allowed." Uros. > > PR target/89021 > * config/i386/mmx.md (sse_movntq): Add SSE2 emulation. > --- > gcc/config/i386/mmx.md | 14 +++++++++----- > 1 file changed, 9 insertions(+), 5 deletions(-) > > diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md > index 0c08aebb071..274e895f51e 100644 > --- a/gcc/config/i386/mmx.md > +++ b/gcc/config/i386/mmx.md > @@ -214,12 +214,16 @@ > }) > > (define_insn "sse_movntq" > - [(set (match_operand:DI 0 "memory_operand" "=m") > - (unspec:DI [(match_operand:DI 1 "register_operand" "y")] > + [(set (match_operand:DI 0 "memory_operand" "=m,m") > + (unspec:DI [(match_operand:DI 1 "register_operand" "y,r")] > UNSPEC_MOVNTQ))] > - "TARGET_SSE || TARGET_3DNOW_A" > - "movntq\t{%1, %0|%0, %1}" > - [(set_attr "type" "mmxmov") > + "(TARGET_MMX || TARGET_MMX_WITH_SSE) > + && (TARGET_SSE || TARGET_3DNOW_A)" > + "@ > + movntq\t{%1, %0|%0, %1} > + movnti\t{%1, %0|%0, %1}" > + [(set_attr "mmx_isa" "native,x64") > + (set_attr "type" "mmxmov,ssemov") > (set_attr "mode" "DI")]) > > ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; > -- > 2.20.1 >