Hello!

Attached patch fixes non-BMI2 shift define-and-split instructions that
remove unnecessary masking of count operand by adding a register
constraints that allows only CX hard register.

2017-12-21  Uros Bizjak  <ubizjak@gmail.com>

    PR target/83467
    * config/i386/i386.md (*ashl<mode>3_mask): Add operand
    constraints to operand 2.
    (*ashl<mode>3_mask_1): Ditto.
    (*<shift_insn><mode>3_mask): Ditto.
    (*<shift_insn><mode>3_mask_1): Ditto.
    (*<rotate_insn><mode>3_mask): Ditto.
    (*<rotate_insn><mode>3_mask_1): Ditto.

testsuite/ChangeLog:

2017-12-21  Uros Bizjak  <ubizjak@gmail.com>

    PR target/83467
    * gcc.target/i386/pr83467-1.c: New test.
    * gcc.target/i386/pr83467-2.c: Ditto.

Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.

Committed to mainline SVN, will be backported to gcc-7 branch.

Uros.