Re: [x86 PATCH] Support logical shifts by (some) integer constants in TImode STV.

[Uros Bizjak <ubizjak@gmail.com>]

On Tue, Aug 2, 2022 at 7:02 PM Roger Sayle <roger@nextmovesoftware.com> wrote:
>
>
> Hi Uros,
>
> > From: Uros Bizjak <ubizjak@gmail.com>
> > Sent: 31 July 2022 18:23
> > To: Roger Sayle <roger@nextmovesoftware.com>
> > On Fri, Jul 29, 2022 at 12:18 AM Roger Sayle <roger@nextmovesoftware.com>
> > wrote:
> > >
> > > This patch improves TImode STV by adding support for logical shifts by
> > > integer constants that are multiples of 8.  For the test case:
> > >
> > > __int128 a, b;
> > > void foo() { a = b << 16; }
> > >
> > > on x86_64, gcc -O2 currently generates:
> > >
> > >         movq    b(%rip), %rax
> > >         movq    b+8(%rip), %rdx
> > >         shldq   $16, %rax, %rdx
> > >         salq    $16, %rax
> > >         movq    %rax, a(%rip)
> > >         movq    %rdx, a+8(%rip)
> > >         ret
> > >
> > > with this patch we now generate:
> > >
> > >         movdqa  b(%rip), %xmm0
> > >         pslldq  $2, %xmm0
> > >         movaps  %xmm0, a(%rip)
> > >         ret
> > >
> > > This patch has been tested on x86_64-pc-linux-gnu with make bootstrap
> > > and make -k check. both with and without --target_board=unix{-m32},
> > > with no new failures.  Ok for mainline?
> > >
> > >
> > > 2022-07-28  Roger Sayle  <roger@nextmovesoftware.com>
> > >
> > > gcc/ChangeLog
> > >         * config/i386/i386-features.cc (compute_convert_gain): Add gain
> > >         for converting suitable TImode shift to a V1TImode shift.
> > >         (timode_scalar_chain::convert_insn): Add support for converting
> > >         suitable ASHIFT and LSHIFTRT.
> > >         (timode_scalar_to_vector_candidate_p): Consider logical shifts
> > >         by integer constants that are multiples of 8 to be candidates.
> > >
> > > gcc/testsuite/ChangeLog
> > >         * gcc.target/i386/sse4_1-stv-7.c: New test case.
> >
> > + case ASHIFT:
> > + case LSHIFTRT:
> > +  /* For logical shifts by constant multiples of 8. */  igain =
> > + optimize_insn_for_size_p () ? COSTS_N_BYTES (4)
> > +      : COSTS_N_INSNS (1);
> >
> > Isn't the conversion an universal win for -O2 as well as for -Os? The conversion
> > to/from XMM register is already accounted for, so for -Os substituting
> > shldq/salq with pslldq should always be a win. I'd expect the cost calculation to
> > be similar to the general_scalar_chain::compute_convert_gain cost calculation
> > with m = 2.
>
> I agree that the terminology is perhaps a little confusing.  The
> compute_convert_gain function calculates the total "gain" from an
> STV chain, summing the igain of each instruction, and performs
> the STV transformation if this total gain is greater than zero.
> Hence positive values are good and negative values are bad.
>
> In this case, of a logical shift by multiple of 8, converting the chain is indeed always
> beneficial, reducing by 4 bytes in size when optimizing for size, and avoiding 1 fast
> instruction when optimizing for speed.  Having a "positive gain of four bytes" sounds bad,
> but in this sense the gain is used as a synonym of "benefit" not "magnitude".
>
> By comparison, shifting by a single bit 128 bit value is always a net loss, requiring
> three addition fast instructions, or 15 extra bytes in size.  However, it's still worth
> considering/capturing these counter-productive (i.e. negative) values, as they
> might be compensated for by other wins in the chain.
>
> Dealing with COSTS_N_BYTES (when optimizing for size) and COSTS_N_INSNS
> (when optimizing for speed) allows much finer granularity.  For example,
> the constant number of bits used in a shift/rotate, or the value of an
> immediate constant in a compare have significant effects on the size/speed
> of scalar vs. vector code, and this isn't (yet) something easily handled by the
> simple "m" approximation used in general_scalar_chain::compute_convert_gain.
>
> See (comment #5 of) PR target/105034 which mentions the need for more
> accurate parameterization of compute_convert_gain (in response to the
> undesirable suggestion of simply disabling STV when optimizing for size).
>
> I hope this explains the above idiom.  Hopefully, things will become clearer
> when support for shifts by other bit counts, and arithmetic shifts, are added
> to this part of the code (STV).  I'll be sure to add more comments.

Thanks for the explanation, I was confused by the differences between
32bit DImode and 64bit TImode costs (these should IMO be quite
similar, so if the TImode cost function is now more precise, DImode
cost function should follow it).

> [Ok for mainline?]

OK. The cost functions are always in need of more accuracy..

Thanks,
Uros.