From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 130595 invoked by alias); 13 May 2017 21:12:45 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 130584 invoked by uid 89); 13 May 2017 21:12:44 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-10.6 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,RCVD_IN_SORBS_SPAM,SPF_PASS autolearn=ham version=3.3.2 spammy=hello! X-HELO: mail-vk0-f44.google.com Received: from mail-vk0-f44.google.com (HELO mail-vk0-f44.google.com) (209.85.213.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 13 May 2017 21:12:43 +0000 Received: by mail-vk0-f44.google.com with SMTP id h16so32358277vkd.2 for ; Sat, 13 May 2017 14:12:45 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=Zy7DV3equ1JaX2NoOE32EKmHHofAatf87jKE8aUAAkg=; b=ASPJN+s/XI0TYHj9FI1f55+nhzRoyLEYmu3n4sEybe2UFmLwnKSb2iKtdVS4xilZ2m RHs7yIBuSb2+LCHJdFRrybcW5kiVtkWac24tXTWjLQmqwh0H4BrHYuFDnbq4RZu3pTbs I5Hv8k5fl4fWy8gXxGOUfVpW8rJvM2dj0P6GsLtxZoXY2chhPhQaGXXwRm5n5RQvQI0r Xbn2qTTfZYqgRSshSvQxEMRvuYQ8NT95Es0G9L08Me1CyblAZKDllHRc3EzJ3pB6BSyN C3Y3LEOg5HZKYQhu+bbhGXDcE67e1urbWuOlokK72JahzsODywJzykI/89R9eZhRjw7f OAvA== X-Gm-Message-State: AODbwcAYb0ZHaFoGTgC/t5MBV4IEkHhkA3mNVwysrex1S2heDTF0Hd1+ 1qS0YC5hfJ/3erbhpKrg39d/9XB9BHG4 X-Received: by 10.31.167.66 with SMTP id q63mr5145674vke.4.1494709964193; Sat, 13 May 2017 14:12:44 -0700 (PDT) MIME-Version: 1.0 Received: by 10.103.48.200 with HTTP; Sat, 13 May 2017 14:12:43 -0700 (PDT) From: Uros Bizjak Date: Sat, 13 May 2017 21:44:00 -0000 Message-ID: Subject: [PATCH, RTL opt]: Ensure that equivalent_reg_at_start rejects registers with mismatched mode To: "gcc-patches@gcc.gnu.org" Content-Type: multipart/mixed; boundary="001a11425c9a75b502054f6e48a8" X-SW-Source: 2017-05/txt/msg01104.txt.bz2 --001a11425c9a75b502054f6e48a8 Content-Type: text/plain; charset="UTF-8" Content-length: 1662 Hello! -mtune=intel is able to copy SFmode value through general registers, resulting in the following sequence: (insn 288 1008 1009 29 (parallel [ (set (reg:DI 4 si [687]) (lshiftrt:DI (reg:DI 4 si [687]) (const_int 32 [0x20]))) (clobber (reg:CC 17 flags)) ]) "ttt.c":41 546 {*lshrdi3_1} (nil)) (insn 1009 288 289 29 (set (reg:DI 2 cx [419]) (reg:DI 4 si [687])) "ttt.c":41 81 {*movdi_internal} (nil)) (insn 289 1009 291 29 (set (reg:SF 21 xmm0 [425]) (reg:SF 2 cx [419])) "ttt.c":41 127 {*movsf_internal} (nil)) (insn 291 289 292 29 (set (reg:CCFPU 17 flags) (compare:CCFPU (reg:SF 21 xmm0 [425]) (reg:SF 27 xmm6 [688]))) "ttt.c":41 51 {*cmpiusf} (expr_list:REG_EQUAL (compare:CCFPU (reg:SF 21 xmm0 [425]) (const_double:SF 0.0 [0x0.0p+0])) (nil))) Looking at compare-elim.c, equivalent_reg_at_start, the function traces the value in %xmm0 to %rsi. So, try_eliminate_compare tries to check if the target supports the compare of (lshiftrt:DI (reg:DI 4 si [687]) (const_int 32 [0x20]))) with (reg:SF 27 xmm6 [688]) which won't fly, since compare operands must have the same modes. Attached patch ensures that the mode of register copy, found by equivalent_reg_at_start equals original mode. 2017-05-13 Uros Bizjak * compare-elim.c (equivalent_reg_at_start): Return NULL_RTX when returned register mode doesn't match original mode. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN as obvious. Uros. --001a11425c9a75b502054f6e48a8 Content-Type: text/plain; charset="US-ASCII"; name="p.diff.txt" Content-Disposition: attachment; filename="p.diff.txt" Content-Transfer-Encoding: base64 X-Attachment-Id: f_j2nrpt2s0 Content-length: 863 SW5kZXg6IGNvbXBhcmUtZWxpbS5jCj09PT09PT09PT09PT09PT09PT09PT09 PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT0K LS0tIGNvbXBhcmUtZWxpbS5jCShyZXZpc2lvbiAyNDgwMDgpCisrKyBjb21w YXJlLWVsaW0uYwkod29ya2luZyBjb3B5KQpAQCAtNTI2LDYgKzUyNiw3IEBA IG1heWJlX3NlbGVjdF9jY19tb2RlIChzdHJ1Y3QgY29tcGFyaXNvbiAqY21w LCBydHgKIHN0YXRpYyBydHgKIGVxdWl2YWxlbnRfcmVnX2F0X3N0YXJ0IChy dHggcmVnLCBydHhfaW5zbiAqZW5kLCBydHhfaW5zbiAqc3RhcnQpCiB7Cisg IG1hY2hpbmVfbW9kZSBvcmlnX21vZGUgPSBHRVRfTU9ERSAocmVnKTsKICAg cnR4X2luc24gKmJiX2hlYWQgPSBCQl9IRUFEIChCTE9DS19GT1JfSU5TTiAo ZW5kKSk7CiAKICAgZm9yIChydHhfaW5zbiAqaW5zbiA9IFBSRVZfSU5TTiAo ZW5kKTsKQEAgLTU3Miw2ICs1NzMsOSBAQCBlcXVpdmFsZW50X3JlZ19hdF9z dGFydCAocnR4IHJlZywgcnR4X2luc24gKmVuZCwgcgogCXJldHVybiBOVUxM X1JUWDsKICAgICB9CiAKKyAgaWYgKEdFVF9NT0RFIChyZWcpICE9IG9yaWdf bW9kZSkKKyAgICByZXR1cm4gTlVMTF9SVFg7CisKICAgcmV0dXJuIHJlZzsK IH0KIAo= --001a11425c9a75b502054f6e48a8--