From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qv1-xf2b.google.com (mail-qv1-xf2b.google.com [IPv6:2607:f8b0:4864:20::f2b]) by sourceware.org (Postfix) with ESMTPS id 81186398780E for ; Wed, 11 Nov 2020 08:45:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 81186398780E Received: by mail-qv1-xf2b.google.com with SMTP id q7so521093qvt.12 for ; Wed, 11 Nov 2020 00:45:28 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to:cc; bh=jdqPKdT5vNbaKAmtesMVxAYdW9zJ3Y2UG+VvGSkDf2A=; b=W902+44uLrfKRRLWD5YiDh4B2foB4QJVNEbiCvYWBKkvoJW38/i/6RXgI3jrK+ov/a tl1TMIxJhdB6WVTMNZa+FkZc/ydEmWvKr75SZjH+kV8HWhU7xxehoxdOOrW+QN3AsQ0c 19CdZYxOW/ue+PTE6WCvocjZ8QT5nORJJZZ8KZJx5S/ql/vAtG/QOzZXpm1BkeJztujp mgUF30FC2AHuZNn9fzjkCPdxnU8GtWVYBRMO18WjiP4kqwa+XwURB9Oni+fZVXh2gfTG IGvMI8onYtLq25pl7jOBZVb2AhRa7yVZoBCDElPdNh5KXUT4gjOQ8y314I/J2gSRyvZA i7rA== X-Gm-Message-State: AOAM531mTQpscJ4hIqtDo+lCnLu9GQ2i21r3fjFYY1IsNdsu7agWqnkh PEdqo5VRj9ghklI8wOW39TuYusoUA8ZHtgBCEWqyehm7tC55EQ== X-Google-Smtp-Source: ABdhPJxvJJNmNQiCd1jnNDC4Zg88F5rXae41UjZUwC/2FZ9TqR4TU0DXgGuEOf9pgxPsDycykrky1opNS2iVYO5n2vc= X-Received: by 2002:a05:6214:a8f:: with SMTP id ev15mr12521835qvb.20.1605084327982; Wed, 11 Nov 2020 00:45:27 -0800 (PST) MIME-Version: 1.0 From: Uros Bizjak Date: Wed, 11 Nov 2020 09:45:16 +0100 Message-ID: Subject: Re: [PATCH] [PR target/97194] [AVX2] Support variable index vec_set. To: "gcc-patches@gcc.gnu.org" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-10.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Nov 2020 08:45:29 -0000 > gcc/ChangeLog: > > PR target/97194 > * config/i386/i386-expand.c (ix86_expand_vector_set_var): New function. > * config/i386/i386-protos.h (ix86_expand_vector_set_var): New Decl. > * config/i386/predicates.md (vec_setm_operand): New predicate, > true for const_int_operand or register_operand under TARGET_AVX2. > * config/i386/sse.md (vec_set): Support both constant > and variable index vec_set. > > gcc/testsuite/ChangeLog: > > * gcc.target/i386/avx2-vec-set-1.c: New test. > * gcc.target/i386/avx2-vec-set-2.c: New test. > * gcc.target/i386/avx512bw-vec-set-1.c: New test. > * gcc.target/i386/avx512bw-vec-set-2.c: New test. > * gcc.target/i386/avx512f-vec-set-2.c: New test. > * gcc.target/i386/avx512vl-vec-set-2.c: New test. +;; True for registers, or const_int_operand, used to vec_setm expander. +(define_predicate "vec_setm_operand" + (ior (and (match_operand 0 "register_operand") + (match_test "TARGET_AVX2")) + (match_code "const_int"))) + ;; True for registers, or 1 or -1. Used to optimize double-word shifts. (define_predicate "reg_or_pm1_operand" (ior (match_operand 0 "register_operand") diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index b153a87fb98..1798e5dea75 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -8098,11 +8098,14 @@ (define_insn "vec_setv2df_0" (define_expand "vec_set" [(match_operand:V 0 "register_operand") (match_operand: 1 "register_operand") - (match_operand 2 "const_int_operand")] + (match_operand 2 "vec_setm_operand")] You need to specify a mode, otherwise a register of any mode can pass here. Uros.