From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 22327 invoked by alias); 18 Nov 2013 20:27:38 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 22286 invoked by uid 89); 18 Nov 2013 20:27:37 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.4 required=5.0 tests=AWL,BAYES_50,FREEMAIL_FROM,RDNS_NONE,SPF_PASS autolearn=no version=3.3.2 X-HELO: mail-oa0-f48.google.com Received: from Unknown (HELO mail-oa0-f48.google.com) (209.85.219.48) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Mon, 18 Nov 2013 20:27:36 +0000 Received: by mail-oa0-f48.google.com with SMTP id n16so7621599oag.7 for ; Mon, 18 Nov 2013 12:27:29 -0800 (PST) MIME-Version: 1.0 X-Received: by 10.182.227.136 with SMTP id sa8mr4427388obc.39.1384806448956; Mon, 18 Nov 2013 12:27:28 -0800 (PST) Received: by 10.182.137.136 with HTTP; Mon, 18 Nov 2013 12:27:28 -0800 (PST) In-Reply-To: References: Date: Mon, 18 Nov 2013 21:57:00 -0000 Message-ID: Subject: Re: [PATCH] Support addsub/subadd as non-isomorphic operations for SLP vectorizer. From: Uros Bizjak To: Cong Hou Cc: "gcc-patches@gcc.gnu.org" , Richard Biener Content-Type: text/plain; charset=ISO-8859-1 X-SW-Source: 2013-11/txt/msg02170.txt.bz2 On Mon, Nov 18, 2013 at 9:15 PM, Cong Hou wrote: >>> This patch adds the support to two non-isomorphic operations addsub >>> and subadd for SLP vectorizer. More non-isomorphic operations can be >>> added later, but the limitation is that operations on even/odd >>> elements should still be isomorphic. Once such an operation is >>> detected, the code of the operation used in vectorized code is stored >>> and later will be used during statement transformation. Two new GIMPLE >>> opeartions VEC_ADDSUB_EXPR and VEC_SUBADD_EXPR are defined. And also >>> new optabs for them. They are also documented. >>> >>> The target supports for SSE/SSE2/SSE3/AVX are added for those two new >>> operations on floating points. SSE3/AVX provides ADDSUBPD and ADDSUBPS >>> instructions. For SSE/SSE2, those two operations are emulated using >>> two instructions (selectively negate then add). >> >> +(define_expand "vec_subadd_v4sf3" >> + [(set (match_operand:V4SF 0 "register_operand") >> + (unspec:V4SF >> + [(match_operand:V4SF 1 "register_operand") >> + (match_operand:V4SF 2 "nonimmediate_operand")] UNSPEC_SUBADD))] >> + "TARGET_SSE" >> +{ >> + if (TARGET_SSE3) >> + emit_insn (gen_sse3_addsubv4sf3 (operands[0], operands[1], operands[2])); >> + else >> + ix86_sse_expand_fp_addsub_operator (true, V4SFmode, operands); >> + DONE; >> +}) >> >> Make the expander pattern look like correspondig sse3 insn and: >> ... >> { >> if (!TARGET_SSE3) >> { >> ix86_sse_expand_fp_...(); >> DONE; >> } >> } >> > > You mean I should write two expanders for SSE and SSE3 respectively? No, please use the same approach as you did for abs2 expander. For !TARGET_SSE3, call the helper function (ix86_sse_expand...), otherwise expand through pattern. Also, it looks to me that you should partially expand in the pattern before calling helper function, mainly to avoid a bunch of "if (...)" at the beginning of the helper function. Uros.