From: Uros Bizjak <ubizjak@gmail.com>
To: "H.J. Lu" <hjl.tools@gmail.com>
Cc: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Subject: [PATCH, testsuite]: Re-enable 64-bit form in gcc.target/i386/ssse3-*.c on AVX targets
Date: Thu, 14 Feb 2019 21:57:00 -0000 [thread overview]
Message-ID: <CAFULd4akrdqArLVcYXRKv4wDsSxT-djo0AzVYnzZhdH-c2zALg@mail.gmail.com> (raw)
In-Reply-To: <CAMe9rOpH6KQNB+9z0zhDxckpVNnG79VVEuLXUR5=ijAs7ZNujA@mail.gmail.com>
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2019-02-14 Uroš Bizjak <ubizjak@gmail.com>
* gcc.target/i386/ssse3-pabsb.c: Re-enable 64-bit form on AVX targets.
* gcc.target/i386/ssse3-pabsd.c: Ditto.
* gcc.target/i386/ssse3-pabsw.c: Ditto.
* gcc.target/i386/ssse3-palignr.c: Ditto.
* gcc.target/i386/ssse3-phaddd.c: Ditto.
* gcc.target/i386/ssse3-phaddsw.c: Ditto.
* gcc.target/i386/ssse3-phaddw.c: Ditto.
* gcc.target/i386/ssse3-phsubd.c: Ditto.
* gcc.target/i386/ssse3-phsubsw.c: Ditto.
* gcc.target/i386/ssse3-phsubw.c: Ditto.
* gcc.target/i386/ssse3-pmaddubsw.c: Ditto.
* gcc.target/i386/ssse3-pmulhrsw.c: Ditto.
* gcc.target/i386/ssse3-pshufb.c: Ditto.
* gcc.target/i386/ssse3-psignb.c: Ditto.
* gcc.target/i386/ssse3-psignd.c: Ditto.
* gcc.target/i386/ssse3-psignw.c: Ditto.
Tested on x86_64-linux-gnu {,-m32} w/ and w/o -mavx.
Committed to mainline SVN.
Uros.
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Index: gcc.target/i386/ssse3-pabsb.c
===================================================================
--- gcc.target/i386/ssse3-pabsb.c (revision 268854)
+++ gcc.target/i386/ssse3-pabsb.c (working copy)
@@ -15,7 +15,6 @@
#include "ssse3-vals.h"
#include <tmmintrin.h>
-#ifndef __AVX__
/* Test the 64-bit form */
static void
ssse3_test_pabsb (int *i1, int *r)
@@ -24,7 +23,6 @@
*(__m64 *) r = _mm_abs_pi8 (t1);
_mm_empty ();
}
-#endif
/* Test the 128-bit form */
static void
@@ -63,12 +61,10 @@
/* Manually compute the result */
compute_correct_result(&vals[i + 0], ck);
-#ifndef __AVX__
/* Run the 64-bit tests */
ssse3_test_pabsb (&vals[i + 0], &r[0]);
ssse3_test_pabsb (&vals[i + 2], &r[2]);
fail += chk_128 (ck, r);
-#endif
/* Run the 128-bit tests */
ssse3_test_pabsb128 (&vals[i + 0], r);
Index: gcc.target/i386/ssse3-pabsd.c
===================================================================
--- gcc.target/i386/ssse3-pabsd.c (revision 268854)
+++ gcc.target/i386/ssse3-pabsd.c (working copy)
@@ -16,7 +16,6 @@
#include <tmmintrin.h>
-#ifndef __AVX__
/* Test the 64-bit form */
static void
ssse3_test_pabsd (int *i1, int *r)
@@ -25,7 +24,6 @@
*(__m64 *) r = _mm_abs_pi32 (t1);
_mm_empty ();
}
-#endif
/* Test the 128-bit form */
static void
@@ -62,12 +60,10 @@
/* Manually compute the result */
compute_correct_result(&vals[i + 0], ck);
-#ifndef __AVX__
/* Run the 64-bit tests */
ssse3_test_pabsd (&vals[i + 0], &r[0]);
ssse3_test_pabsd (&vals[i + 2], &r[2]);
fail += chk_128 (ck, r);
-#endif
/* Run the 128-bit tests */
ssse3_test_pabsd128 (&vals[i + 0], r);
Index: gcc.target/i386/ssse3-pabsw.c
===================================================================
--- gcc.target/i386/ssse3-pabsw.c (revision 268854)
+++ gcc.target/i386/ssse3-pabsw.c (working copy)
@@ -16,7 +16,6 @@
#include <tmmintrin.h>
-#ifndef __AVX__
/* Test the 64-bit form */
static void
ssse3_test_pabsw (int *i1, int *r)
@@ -25,7 +24,6 @@
*(__m64 *) r = _mm_abs_pi16 (t1);
_mm_empty ();
}
-#endif
/* Test the 128-bit form */
static void
@@ -64,12 +62,10 @@
/* Manually compute the result */
compute_correct_result (&vals[i + 0], ck);
-#ifndef __AVX__
/* Run the 64-bit tests */
ssse3_test_pabsw (&vals[i + 0], &r[0]);
ssse3_test_pabsw (&vals[i + 2], &r[2]);
fail += chk_128 (ck, r);
-#endif
/* Run the 128-bit tests */
ssse3_test_pabsw128 (&vals[i + 0], r);
Index: gcc.target/i386/ssse3-palignr.c
===================================================================
--- gcc.target/i386/ssse3-palignr.c (revision 268854)
+++ gcc.target/i386/ssse3-palignr.c (working copy)
@@ -17,7 +17,6 @@
#include <tmmintrin.h>
#include <string.h>
-#ifndef __AVX__
/* Test the 64-bit form */
static void
ssse3_test_palignr (int *i1, int *i2, unsigned int imm, int *r)
@@ -82,7 +81,6 @@
_mm_empty();
}
-#endif
/* Test the 128-bit form */
static void
@@ -214,7 +212,6 @@
bout[i] = buf[imm + i];
}
-#ifndef __AVX__
static void
compute_correct_result_64 (int *i1, int *i2, unsigned int imm, int *r)
{
@@ -242,7 +239,6 @@
else
bout[i + 8] = buf[imm + i];
}
-#endif
static void
TEST (void)
@@ -256,7 +252,6 @@
for (i = 0; i < 256; i += 8)
for (imm = 0; imm < 100; imm++)
{
-#ifndef __AVX__
/* Manually compute the result */
compute_correct_result_64 (&vals[i + 0], &vals[i + 4], imm, ck);
@@ -264,7 +259,6 @@
ssse3_test_palignr (&vals[i + 0], &vals[i + 4], imm, &r[0]);
ssse3_test_palignr (&vals[i + 2], &vals[i + 6], imm, &r[2]);
fail += chk_128 (ck, r);
-#endif
/* Recompute the results for 128-bits */
compute_correct_result_128 (&vals[i + 0], &vals[i + 4], imm, ck);
Index: gcc.target/i386/ssse3-phaddd.c
===================================================================
--- gcc.target/i386/ssse3-phaddd.c (revision 268854)
+++ gcc.target/i386/ssse3-phaddd.c (working copy)
@@ -16,7 +16,6 @@
#include <tmmintrin.h>
-#ifndef __AVX__
/* Test the 64-bit form */
static void
ssse3_test_phaddd (int *i1, int *i2, int *r)
@@ -26,7 +25,6 @@
*(__m64 *) r = _mm_hadd_pi32 (t1, t2);
_mm_empty();
}
-#endif
/* Test the 128-bit form */
static void
@@ -64,12 +62,10 @@
/* Manually compute the result */
compute_correct_result (&vals[i + 0], &vals[i + 4], ck);
-#ifndef __AVX__
/* Run the 64-bit tests */
ssse3_test_phaddd (&vals[i + 0], &vals[i + 2], &r[0]);
ssse3_test_phaddd (&vals[i + 4], &vals[i + 6], &r[2]);
fail += chk_128 (ck, r);
-#endif
/* Run the 128-bit tests */
ssse3_test_phaddd128 (&vals[i + 0], &vals[i + 4], r);
Index: gcc.target/i386/ssse3-phaddsw.c
===================================================================
--- gcc.target/i386/ssse3-phaddsw.c (revision 268854)
+++ gcc.target/i386/ssse3-phaddsw.c (working copy)
@@ -16,7 +16,6 @@
#include <tmmintrin.h>
-#ifndef __AVX__
/* Test the 64-bit form */
static void
ssse3_test_phaddsw (int *i1, int *i2, int *r)
@@ -26,7 +25,6 @@
*(__m64 *) r = _mm_hadds_pi16 (t1, t2);
_mm_empty ();
}
-#endif
/* Test the 128-bit form */
static void
@@ -78,12 +76,10 @@
/* Manually compute the result */
compute_correct_result (&vals[i + 0], &vals[i + 4], ck);
-#ifndef __AVX__
/* Run the 64-bit tests */
ssse3_test_phaddsw (&vals[i + 0], &vals[i + 2], &r[0]);
ssse3_test_phaddsw (&vals[i + 4], &vals[i + 6], &r[2]);
fail += chk_128 (ck, r);
-#endif
/* Run the 128-bit tests */
ssse3_test_phaddsw128 (&vals[i + 0], &vals[i + 4], r);
Index: gcc.target/i386/ssse3-phaddw.c
===================================================================
--- gcc.target/i386/ssse3-phaddw.c (revision 268854)
+++ gcc.target/i386/ssse3-phaddw.c (working copy)
@@ -16,7 +16,6 @@
#include <tmmintrin.h>
-#ifndef __AVX__
/* Test the 64-bit form */
static void
ssse3_test_phaddw (int *i1, int *i2, int *r)
@@ -26,7 +25,6 @@
*(__m64 *) r = _mm_hadd_pi16 (t1, t2);
_mm_empty ();
}
-#endif
/* Test the 128-bit form */
static void
@@ -67,12 +65,10 @@
/* Manually compute the result */
compute_correct_result (&vals[i + 0], &vals[i + 4], ck);
-#ifndef __AVX__
/* Run the 64-bit tests */
ssse3_test_phaddw (&vals[i + 0], &vals[i + 2], &r[0]);
ssse3_test_phaddw (&vals[i + 4], &vals[i + 6], &r[2]);
fail += chk_128 (ck, r);
-#endif
/* Run the 128-bit tests */
ssse3_test_phaddw128 (&vals[i + 0], &vals[i + 4], r);
Index: gcc.target/i386/ssse3-phsubd.c
===================================================================
--- gcc.target/i386/ssse3-phsubd.c (revision 268854)
+++ gcc.target/i386/ssse3-phsubd.c (working copy)
@@ -16,7 +16,6 @@
#include <tmmintrin.h>
-#ifndef __AVX__
/* Test the 64-bit form */
static void
ssse3_test_phsubd (int *i1, int *i2, int *r)
@@ -26,7 +25,6 @@
*(__m64 *) r = _mm_hsub_pi32(t1, t2);
_mm_empty ();
}
-#endif
/* Test the 128-bit form */
static void
@@ -63,12 +61,10 @@
/* Manually compute the result */
compute_correct_result (&vals[i + 0], &vals[i + 4], ck);
-#ifndef __AVX__
/* Run the 64-bit tests */
ssse3_test_phsubd (&vals[i + 0], &vals[i + 2], &r[0]);
ssse3_test_phsubd (&vals[i + 4], &vals[i + 6], &r[2]);
fail += chk_128 (ck, r);
-#endif
/* Run the 128-bit tests */
ssse3_test_phsubd128 (&vals[i + 0], &vals[i + 4], r);
Index: gcc.target/i386/ssse3-phsubsw.c
===================================================================
--- gcc.target/i386/ssse3-phsubsw.c (revision 268854)
+++ gcc.target/i386/ssse3-phsubsw.c (working copy)
@@ -16,7 +16,6 @@
#include <tmmintrin.h>
-#ifndef __AVX__
/* Test the 64-bit form */
static void
ssse3_test_phsubsw (int *i1, int *i2, int *r)
@@ -28,7 +27,6 @@
_mm_empty ();
}
-#endif
/* Test the 128-bit form */
static void
@@ -81,12 +79,10 @@
/* Manually compute the result */
compute_correct_result (&vals[i + 0], &vals[i + 4], ck);
-#ifndef __AVX__
/* Run the 64-bit tests */
ssse3_test_phsubsw (&vals[i + 0], &vals[i + 2], &r[0]);
ssse3_test_phsubsw (&vals[i + 4], &vals[i + 6], &r[2]);
fail += chk_128 (ck, r);
-#endif
/* Run the 128-bit tests */
ssse3_test_phsubsw128 (&vals[i + 0], &vals[i + 4], r);
Index: gcc.target/i386/ssse3-phsubw.c
===================================================================
--- gcc.target/i386/ssse3-phsubw.c (revision 268854)
+++ gcc.target/i386/ssse3-phsubw.c (working copy)
@@ -15,7 +15,6 @@
#include <tmmintrin.h>
-#ifndef __AVX__
/* Test the 64-bit form */
static void
ssse3_test_phsubw (int *i1, int *i2, int *r)
@@ -25,7 +24,6 @@
*(__m64 *) r = _mm_hsub_pi16 (t1, t2);
_mm_empty ();
}
-#endif
/* Test the 128-bit form */
static void
@@ -66,12 +64,10 @@
/* Manually compute the result */
compute_correct_result (&vals[i + 0], &vals[i + 4], ck);
-#ifndef __AVX__
/* Run the 64-bit tests */
ssse3_test_phsubw (&vals[i + 0], &vals[i + 2], &r[0]);
ssse3_test_phsubw (&vals[i + 4], &vals[i + 6], &r[2]);
fail += chk_128 (ck, r);
-#endif
/* Run the 128-bit tests */
ssse3_test_phsubw128 (&vals[i + 0], &vals[i + 4], r);
Index: gcc.target/i386/ssse3-pmaddubsw.c
===================================================================
--- gcc.target/i386/ssse3-pmaddubsw.c (revision 268854)
+++ gcc.target/i386/ssse3-pmaddubsw.c (working copy)
@@ -16,7 +16,6 @@
#include <tmmintrin.h>
-#ifndef __AVX__
/* Test the 64-bit form */
static void
ssse3_test_pmaddubsw (int *i1, int *i2, int *r)
@@ -26,7 +25,6 @@
*(__m64 *) r = _mm_maddubs_pi16 (t1, t2);
_mm_empty ();
}
-#endif
/* Test the 128-bit form */
static void
@@ -81,12 +79,10 @@
/* Manually compute the result */
compute_correct_result (&vals[i + 0], &vals[i + 4], ck);
-#ifndef __AVX__
/* Run the 64-bit tests */
ssse3_test_pmaddubsw (&vals[i + 0], &vals[i + 4], &r[0]);
ssse3_test_pmaddubsw (&vals[i + 2], &vals[i + 6], &r[2]);
fail += chk_128 (ck, r);
-#endif
/* Run the 128-bit tests */
ssse3_test_pmaddubsw128 (&vals[i + 0], &vals[i + 4], r);
Index: gcc.target/i386/ssse3-pmulhrsw.c
===================================================================
--- gcc.target/i386/ssse3-pmulhrsw.c (revision 268854)
+++ gcc.target/i386/ssse3-pmulhrsw.c (working copy)
@@ -16,7 +16,6 @@
#include <tmmintrin.h>
-#ifndef __AVX__
/* Test the 64-bit form */
static void
ssse3_test_pmulhrsw (int *i1, int *i2, int *r)
@@ -26,7 +25,6 @@
*(__m64 *) r = _mm_mulhrs_pi16 (t1, t2);
_mm_empty ();
}
-#endif
/* Test the 128-bit form */
static void
@@ -68,12 +66,10 @@
/* Manually compute the result */
compute_correct_result (&vals[i + 0], &vals[i + 4], ck);
-#ifndef __AVX__
/* Run the 64-bit tests */
ssse3_test_pmulhrsw (&vals[i + 0], &vals[i + 4], &r[0]);
ssse3_test_pmulhrsw (&vals[i + 2], &vals[i + 6], &r[2]);
fail += chk_128 (ck, r);
-#endif
/* Run the 128-bit tests */
ssse3_test_pmulhrsw128 (&vals[i + 0], &vals[i + 4], r);
Index: gcc.target/i386/ssse3-pshufb.c
===================================================================
--- gcc.target/i386/ssse3-pshufb.c (revision 268854)
+++ gcc.target/i386/ssse3-pshufb.c (working copy)
@@ -16,7 +16,6 @@
#include <tmmintrin.h>
-#ifndef __AVX__
/* Test the 64-bit form */
static void
ssse3_test_pshufb (int *i1, int *i2, int *r)
@@ -26,7 +25,6 @@
*(__m64 *)r = _mm_shuffle_pi8 (t1, t2);
_mm_empty ();
}
-#endif
/* Test the 128-bit form */
static void
@@ -38,7 +36,6 @@
*(__m128i *)r = _mm_shuffle_epi8 (t1, t2);
}
-#ifndef __AVX__
/* Routine to manually compute the results */
static void
compute_correct_result_64 (int *i1, int *i2, int *r)
@@ -60,7 +57,6 @@
bout[i] = b1[8 + (select & 0x7)];
}
}
-#endif
static void
compute_correct_result_128 (int *i1, int *i2, int *r)
@@ -91,7 +87,6 @@
for (i = 0; i < 256; i += 8)
{
-#ifndef __AVX__
/* Manually compute the result */
compute_correct_result_64 (&vals[i + 0], &vals[i + 4], ck);
@@ -99,7 +94,6 @@
ssse3_test_pshufb (&vals[i + 0], &vals[i + 4], &r[0]);
ssse3_test_pshufb (&vals[i + 2], &vals[i + 6], &r[2]);
fail += chk_128 (ck, r);
-#endif
/* Recompute the result for 128-bits */
compute_correct_result_128 (&vals[i + 0], &vals[i + 4], ck);
Index: gcc.target/i386/ssse3-psignb.c
===================================================================
--- gcc.target/i386/ssse3-psignb.c (revision 268854)
+++ gcc.target/i386/ssse3-psignb.c (working copy)
@@ -15,7 +15,6 @@
#include <tmmintrin.h>
-#ifndef __AVX__
/* Test the 64-bit form */
static void
ssse3_test_psignb (int *i1, int *i2, int *r)
@@ -25,7 +24,6 @@
*(__m64 *) r = _mm_sign_pi8 (t1, t2);
_mm_empty ();
}
-#endif
/* Test the 128-bit form */
static void
@@ -68,12 +66,10 @@
/* Manually compute the result */
compute_correct_result (&vals[i + 0], &vals[i + 4], ck);
-#ifndef __AVX__
/* Run the 64-bit tests */
ssse3_test_psignb (&vals[i + 0], &vals[i + 4], &r[0]);
ssse3_test_psignb (&vals[i + 2], &vals[i + 6], &r[2]);
fail += chk_128 (ck, r);
-#endif
/* Run the 128-bit tests */
ssse3_test_psignb128 (&vals[i + 0], &vals[i + 4], r);
Index: gcc.target/i386/ssse3-psignd.c
===================================================================
--- gcc.target/i386/ssse3-psignd.c (revision 268854)
+++ gcc.target/i386/ssse3-psignd.c (working copy)
@@ -15,7 +15,6 @@
#include <tmmintrin.h>
-#ifndef __AVX__
/* Test the 64-bit form */
static void
ssse3_test_psignd (int *i1, int *i2, int *r)
@@ -25,7 +24,6 @@
*(__m64 *) r = _mm_sign_pi32 (t1, t2);
_mm_empty ();
}
-#endif
/* Test the 128-bit form */
static void
@@ -65,12 +63,10 @@
/* Manually compute the result */
compute_correct_result (&vals[i + 0], &vals[i + 4], ck);
-#ifndef __AVX__
/* Run the 64-bit tests */
ssse3_test_psignd (&vals[i + 0], &vals[i + 4], &r[0]);
ssse3_test_psignd (&vals[i + 2], &vals[i + 6], &r[2]);
fail += chk_128 (ck, r);
-#endif
/* Run the 128-bit tests */
ssse3_test_psignd128 (&vals[i + 0], &vals[i + 4], r);
Index: gcc.target/i386/ssse3-psignw.c
===================================================================
--- gcc.target/i386/ssse3-psignw.c (revision 268854)
+++ gcc.target/i386/ssse3-psignw.c (working copy)
@@ -15,7 +15,6 @@
#include <tmmintrin.h>
-#ifndef __AVX__
/* Test the 64-bit form */
static void
ssse3_test_psignw (int *i1, int *i2, int *r)
@@ -25,7 +24,6 @@
*(__m64 *) r = _mm_sign_pi16 (t1, t2);
_mm_empty ();
}
-#endif
/* Test the 128-bit form */
static void
@@ -68,12 +66,10 @@
/* Manually compute the result */
compute_correct_result (&vals[i + 0], &vals[i + 4], ck);
-#ifndef __AVX__
/* Run the 64-bit tests */
ssse3_test_psignw (&vals[i + 0], &vals[i + 4], &r[0]);
ssse3_test_psignw (&vals[i + 2], &vals[i + 6], &r[2]);
fail += chk_128 (ck, r);
-#endif
/* Run the 128-bit tests */
ssse3_test_psignw128 (&vals[i + 0], &vals[i + 4], r);
next prev parent reply other threads:[~2019-02-14 21:57 UTC|newest]
Thread overview: 61+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-14 12:31 [PATCH 00/40] V5: Emulate MMX intrinsics with SSE H.J. Lu
2019-02-14 12:31 ` [PATCH 14/40] i386: Emulate MMX sse_cvtps2pi/sse_cvttps2pi " H.J. Lu
2019-02-14 12:31 ` [PATCH 04/40] i386: Emulate MMX plusminus/sat_plusminus " H.J. Lu
2019-02-14 12:31 ` [PATCH 03/40] i386: Emulate MMX punpcklXX/punpckhXX with SSE punpcklXX H.J. Lu
2019-02-14 12:31 ` [PATCH 23/40] i386: Emulate MMX mmx_uavgv4hi3 with SSE H.J. Lu
2019-02-14 12:31 ` [PATCH 13/40] i386: Emulate MMX pshufw " H.J. Lu
2019-02-14 12:31 ` [PATCH 35/40] i386: Allow MMXMODE moves with TARGET_MMX_WITH_SSE H.J. Lu
2019-02-14 12:31 ` [PATCH 17/40] i386: Emulate MMX mmx_pinsrw with SSE H.J. Lu
2019-02-14 12:31 ` [PATCH 05/40] i386: Emulate MMX mulv4hi3 " H.J. Lu
2019-02-14 12:31 ` [PATCH 07/40] i386: Emulate MMX mmx_pmaddwd " H.J. Lu
2019-02-14 12:31 ` [PATCH 10/40] i386: Emulate MMX mmx_andnot<mode>3 " H.J. Lu
2019-02-14 12:31 ` [PATCH 16/40] i386: Emulate MMX mmx_pextrw " H.J. Lu
2019-02-14 12:31 ` [PATCH 40/40] i386: Also enable SSSE3 __m64 tests in 64-bit mode H.J. Lu
2019-02-14 20:21 ` Uros Bizjak
2019-02-14 20:43 ` Uros Bizjak
2019-02-14 20:56 ` H.J. Lu
2019-02-14 21:57 ` Uros Bizjak [this message]
2019-02-14 12:31 ` [PATCH 31/40] i386: Emulate MMX pshufb with SSE version H.J. Lu
2019-02-14 14:21 ` Uros Bizjak
2019-02-14 12:31 ` [PATCH 02/40] i386: Emulate MMX packsswb/packssdw/packuswb with SSE2 H.J. Lu
2019-02-14 12:31 ` [PATCH 12/40] i386: Emulate MMX vec_dupv2si with SSE H.J. Lu
2019-02-14 12:31 ` [PATCH 06/40] i386: Emulate MMX smulv4hi3_highpart " H.J. Lu
2019-02-14 12:31 ` [PATCH 08/40] i386: Emulate MMX ashr<mode>3/<shift_insn><mode>3 " H.J. Lu
2019-02-14 14:04 ` Uros Bizjak
2019-02-14 12:31 ` [PATCH 20/40] i386: Emulate MMX mmx_umulv4hi3_highpart " H.J. Lu
2019-02-14 12:33 ` [PATCH 21/40] i386: Emulate MMX maskmovq with SSE2 maskmovdqu H.J. Lu
2019-02-14 12:33 ` [PATCH 24/40] i386: Emulate MMX mmx_psadbw with SSE H.J. Lu
2019-02-14 12:33 ` [PATCH 29/40] i386: Emulate MMX ssse3_pmaddubsw " H.J. Lu
2019-02-14 12:33 ` [PATCH 28/40] i386: Emulate MMX ssse3_ph<plusminus_mnemonic>dv2si3 " H.J. Lu
2019-02-14 12:33 ` [PATCH 09/40] i386: Emulate MMX <any_logic><mode>3 " H.J. Lu
2019-02-14 12:33 ` [PATCH 11/40] i386: Emulate MMX mmx_eq/mmx_gt<mode>3 " H.J. Lu
2019-02-14 12:33 ` [PATCH 32/40] i386: Emulate MMX ssse3_psign<mode>3 " H.J. Lu
2019-02-14 12:33 ` [PATCH 01/40] i386: Allow MMX register modes in SSE registers H.J. Lu
2019-02-14 12:33 ` [PATCH 30/40] i386: Emulate MMX ssse3_pmulhrswv4hi3 with SSE H.J. Lu
2019-02-14 12:33 ` [PATCH 15/40] i386: Emulate MMX sse_cvtpi2ps " H.J. Lu
2019-02-14 14:14 ` Uros Bizjak
2019-02-14 12:33 ` [PATCH 38/40] i386: Enable TM MMX intrinsics with SSE2 H.J. Lu
2019-02-14 12:33 ` [PATCH 36/40] i386: Allow MMX vector expanders with TARGET_MMX_WITH_SSE H.J. Lu
2019-02-14 12:33 ` [PATCH 34/40] i386: Emulate MMX abs<mode>2 with SSE H.J. Lu
2019-02-14 12:33 ` [PATCH 25/40] i386: Emulate MMX movntq with SSE2 movntidi H.J. Lu
2019-02-14 14:17 ` Uros Bizjak
2019-02-14 12:33 ` [PATCH 37/40] i386: Allow MMX intrinsic emulation with SSE H.J. Lu
2019-02-14 20:07 ` Uros Bizjak
2019-02-14 20:50 ` H.J. Lu
2019-02-14 20:54 ` Uros Bizjak
2019-02-14 21:02 ` H.J. Lu
2019-02-14 22:57 ` Uros Bizjak
2019-02-14 23:13 ` H.J. Lu
2019-02-14 23:14 ` H.J. Lu
2019-02-14 23:21 ` Uros Bizjak
2019-02-14 23:24 ` H.J. Lu
2019-02-15 12:04 ` Uros Bizjak
2019-02-14 12:33 ` [PATCH 27/40] i386: Emulate MMX ssse3_ph<plusminus_mnemonic>wv4hi3 " H.J. Lu
2019-02-14 12:33 ` [PATCH 22/40] i386: Emulate MMX mmx_uavgv8qi3 " H.J. Lu
2019-02-14 12:33 ` [PATCH 39/40] i386: Add tests for MMX intrinsic emulations " H.J. Lu
2019-02-15 12:21 ` Uros Bizjak
2019-02-14 12:33 ` [PATCH 18/40] i386: Emulate MMX V4HI smaxmin/V8QI umaxmin " H.J. Lu
2019-02-14 12:33 ` [PATCH 19/40] i386: Emulate MMX mmx_pmovmskb " H.J. Lu
2019-02-14 12:33 ` [PATCH 26/40] i386: Emulate MMX umulv1siv1di3 with SSE2 H.J. Lu
2019-02-14 12:33 ` [PATCH 33/40] i386: Emulate MMX ssse3_palignrdi with SSE H.J. Lu
2019-02-14 18:18 ` [PATCH 41/40] Prevent allocation of MMX registers with TARGET_MMX_WITH_SSE Uros Bizjak
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