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From: Uros Bizjak <ubizjak@gmail.com>
Date: Mon, 05 Aug 2019 19:35:00 -0000
Message-ID: <CAFULd4aru2W_fb8mW6U-Ags5KHsJVZgyXypoe+COAwfiSzWcSg@mail.gmail.com>
Subject: Re: [PATCH][RFC][x86] Fix PR91154, add SImode smax, allow SImode add in SSE regs
To: Richard Biener <rguenther@suse.de>
Cc: Jakub Jelinek <jakub@redhat.com>, "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Content-Type: text/plain; charset="UTF-8"
X-SW-Source: 2019-08/txt/msg00300.txt.bz2

On Mon, Aug 5, 2019 at 3:29 PM Richard Biener <rguenther@suse.de> wrote:

> > > > > > > (define_mode_iterator MAXMIN_IMODE [SI "TARGET_SSE4_1"] [DI "TARGET_AVX512F"])
> > > > > > >
> > > > > > > and then we need to split DImode for 32bits, too.
> > > > > >
> > > > > > For now, please add "TARGET_64BIT && TARGET_AVX512F" for DImode
> > > > > > condition, I'll provide _doubleword splitter later.
> > > > >
> > > > > Shouldn't that be TARGET_AVX512VL instead?  Or does the insn use %g0 etc.
> > > > > to force use of %zmmN?
> > > >
> > > > It generates V4SI mode, so - yes, AVX512VL.
> > >
> > >     case SMAX:
> > >     case SMIN:
> > >     case UMAX:
> > >     case UMIN:
> > >       if ((mode == DImode && (!TARGET_64BIT || !TARGET_AVX512VL))
> > >           || (mode == SImode && !TARGET_SSE4_1))
> > >         return false;
> > >
> > > so there's no way to use AVX512VL for 32bit?
> >
> > There is a way, but on 32bit targets, we need to split DImode
> > operation to a sequence of SImode operations for unconverted pattern.
> > This is of course doable, but somehow more complex than simply
> > emitting a DImode compare + DImode cmove, which is what current
> > splitter does. So, a follow-up task.
>
> Ah, OK.  So for the above condition we can elide the !TARGET_64BIT
> check we just need to properly split if we enable the scalar minmax
> pattern for DImode on 32bits, the STV conversion would go fine.

Yes, that is correct.

Uros.