From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 15776 invoked by alias); 26 Oct 2018 07:39:23 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 15766 invoked by uid 89); 26 Oct 2018 07:39:22 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-3.3 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-it1-f196.google.com Received: from mail-it1-f196.google.com (HELO mail-it1-f196.google.com) (209.85.166.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 26 Oct 2018 07:39:21 +0000 Received: by mail-it1-f196.google.com with SMTP id q70-v6so534886itb.3 for ; Fri, 26 Oct 2018 00:39:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=cgcPX8fmsV/V1P2ldIlpSxAXiKm/f83TWl6KIgAB8Xw=; b=X4ig26RiMDJmLJH+CXBpWHmrKSOBhpHV+iNOcpKubiFbGNCntvr18XmL3fWR0ohkRm 3EpM8chyAysqfthi74uruaRhiy7zP6vdG7xBqZLZV4gX8dbMRxjl/bj3RnpY0FHBDWpT 00PcI8D29lSortuVZpKJ2fLSSpsnfylWCwhfVSMDGYVqQxb/DSB/NuSTbDQX80yEXzwC VwxmjDl785Stlb90lXC/CcAttVMUl3eUvsHHF5M5QkUhHgGW0iIs7MHBtkmdZjPE0dkw YonvR8Y6iulpp54fTqcy9tS8UvBYXD2AlObyBo++3unk2BdSCNERS8v/po5nL2/N/MJG 8lYg== MIME-Version: 1.0 References: In-Reply-To: From: Uros Bizjak Date: Fri, 26 Oct 2018 08:41:00 -0000 Message-ID: Subject: Re: V4 [PATCH] x86: Add pmovzx/pmovsx patterns with memory operands To: "H. J. Lu" Cc: "gcc-patches@gcc.gnu.org" , Eric Botcazou Content-Type: text/plain; charset="UTF-8" X-SW-Source: 2018-10/txt/msg01670.txt.bz2 On Fri, Oct 26, 2018 at 9:37 AM Uros Bizjak wrote: > > On Fri, Oct 26, 2018 at 9:35 AM Uros Bizjak wrote: > > > > On Fri, Oct 26, 2018 at 9:19 AM H.J. Lu wrote: > > > > > > On 10/25/18, Uros Bizjak wrote: > > > > On Fri, Oct 26, 2018 at 8:07 AM H.J. Lu wrote: > > > >> > > > >> Many x86 pmovzx/pmovsx instructions with memory operands are modeled in > > > >> a wrong way. For example: > > > >> > > > >> (define_insn "sse4_1_v8qiv8hi2" > > > >> [(set (match_operand:V8HI 0 "register_operand" "=Yr,*x,v") > > > >> (any_extend:V8HI > > > >> (vec_select:V8QI > > > >> (match_operand:V16QI 1 "nonimmediate_operand" "Yrm,*xm,vm") > > > >> (parallel [(const_int 0) (const_int 1) > > > >> (const_int 2) (const_int 3) > > > >> (const_int 4) (const_int 5) > > > >> (const_int 6) (const_int 7)]))))] > > > >> > > > >> should be defind for memory operands as: > > > >> > > > >> (define_insn "sse4_1_v8qiv8hi2" > > > >> [(set (match_operand:V8HI 0 "register_operand" "=Yr,*x,v") > > > >> (any_extend:V8HI > > > >> (match_operand:V8QI "memory_operand" "m,m,m")))] > > > >> > > > >> This set of patches updates them to > > > >> > > > >> (define_insn "sse4_1_v8qiv8hi2" > > > >> [(set (match_operand:V8HI 0 "register_operand" "=Yr,*x,v") > > > >> (any_extend:V8HI > > > >> (vec_select:V8QI > > > >> (match_operand:V16QI 1 "nonimmediate_operand" "Yr,*x,v") > > > >> (parallel [(const_int 0) (const_int 1) > > > >> (const_int 2) (const_int 3) > > > >> (const_int 4) (const_int 5) > > > >> (const_int 6) (const_int 7)]))))] > > > >> > > > >> (define_insn "*sse4_1_v8qiv8hi2_1" > > > >> [(set (match_operand:V8HI 0 "register_operand" "=Yr,*x,v") > > > >> (any_extend:V8HI > > > >> (match_operand:V8QI "subreg_memory_operand" "m,m,m")))] > > > >> > > > >> with a splitter: > > > >> > > > >> (define_insn_and_split "*sse4_1_v8qiv8hi2_2" > > > >> [(set (match_operand:V8HI 0 "register_operand" "=Yr,*x,v") > > > > > > > > No constraints needed for pre-reload splitter. > > > > > > > >> (any_extend:V8HI > > > >> (vec_select:V8QI > > > >> (subreg:V16QI > > > >> (vec_concat:V2DI > > > >> (match_operand:DI 1 "memory_operand" "m,*m,m") > > > >> (const_int 0)) 0) > > > >> (parallel [(const_int 0) (const_int 1) > > > >> (const_int 2) (const_int 3) > > > >> (const_int 4) (const_int 5) > > > >> (const_int 6) (const_int 7)]))))] > > > >> "TARGET_SSE4_1 && && > > > >> " > > > >> "#" > > > >> "&& can_create_pseudo_p ()" > > > >> [(set (match_dup 0) (match_dup 1))] > > > > > > > > [(set (match_dup 0) > > > > (any_extend:V8HI (match_dup 1)))] > > > > > > > >> { > > > >> operands[1] = gen_rtx_ (V8HImode, > > > >> gen_rtx_SUBREG (V8QImode, > > > >> operands[1], 0)); > > > >> }) > > > > > > > > Don't create subregs of memory. Use adjust_address_nv. > > > > > > Here is the updated patch. > > > > > with a splitter: > > > > > > (define_insn_and_split "*sse4_1_v8qiv8hi2_2" > > > [(set (match_operand:V8HI 0 "register_operand") > > > (any_extend:V8HI > > > (vec_select:V8QI > > > (subreg:V16QI > > > (vec_concat:V2DI > > > (match_operand:DI 1 "memory_operand") > > > (const_int 0)) 0) > > > (parallel [(const_int 0) (const_int 1) > > > (const_int 2) (const_int 3) > > > (const_int 4) (const_int 5) > > > (const_int 6) (const_int 7)]))))] > > > "TARGET_SSE4_1 && && " > > > "#" > > > "&& can_create_pseudo_p ()" > > > > "can_create_pseudo_p ()" should go to the insn constraint and "&& 1" > > should be used for split constraint. Both, insn and splitter are valid > > only before reload. > > > > > [(set (match_dup 0) > > > (any_extend:V8HI (match_dup 1)))] > > > { > > > operands[1] = adjust_address_nv (operands[1], V8QImode, 0); > > > }) > > > > Please use double quotes for one-line preparation statement. > > > > > (any_extend:V4SI > > > (match_operand:V4HI 1 "memory_operand" "m,*m,m")))] > > > > Please remove star in front of memory constraint. > > > > OK with the above changes. > > Oh, and you should remove "q" and "k" operand modifiers in all old patterns. Well, the new ones, obviously. Uros.