From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yb1-xb33.google.com (mail-yb1-xb33.google.com [IPv6:2607:f8b0:4864:20::b33]) by sourceware.org (Postfix) with ESMTPS id 2174F3858D28 for ; Mon, 7 Nov 2022 09:30:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 2174F3858D28 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-yb1-xb33.google.com with SMTP id r3so12872989yba.5 for ; Mon, 07 Nov 2022 01:30:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=CnEVQPjRz3CsziseEcyQ56Y7c6gJcNd+FPW5jKt9y5g=; b=a5j8+sySpal5IdlXySLkYPEq6Gsjth7/qRdl4JblTdG9orSINjKQE/Xd3v6cry1KWs BpjXY4FlnehEzFCLmopfIds/ab4mIxfxN2fWfHiQUfsrGiN95kLMLv8WH2F4a+OiAFgS rDQT8lLOl24uLsYnQFHuVZqlV3pU1T+IQr4vtx2Du/g6qbCy4xeoGlQkDCu5jxJxAkzy qp3wP6mUhj7TkjtIwQ6YjmhlkiRikvPcUtyMTtOKFAXBJ+XcXdp1/u3SYEG6aDl/8UJS enp8mpHeUX+rjFtwY7P7xnCizTdjre0xR8QLqDg5tV2x63KfG/SNWGKbiwUugfxXHUOI lyOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=CnEVQPjRz3CsziseEcyQ56Y7c6gJcNd+FPW5jKt9y5g=; b=DG/28DI/HosXrRxy0Qlp724EFo7gI93/BxwV0X909/gUtPMUyYYr1wGIfe+ps9ap6F oQgWOVEJMHNLZwdf/6+Yw7GcqCJwZumubq05t9d538O760K9IQJpWJ+v1Ys5SjnQsTcB oHY8MJclzh9i7MANExNRepEMhBcA+h7N4Cwl/g3QQrrA6EH6ySyWkG1OLtFHCQab+t2n DqF6BAF1H1DKvdHN1F6Qalq35vW1u7GQgyC0Hrz/xH4k7faPoXFk2wEl7NxmX5WQ2YyU U31mHOg/T1Cin9uvHYy3KgvoK0vWt1AD3+Nla8ddM63zYvknjWVH3TFiof3RTKM4Yaft x7Uw== X-Gm-Message-State: ANoB5pnc+bXbNatbKbFS1jr9MH5EB+mszTkxKRPPpJNzQi6u3GTBDlvR 351CSRN6rAJVs8kf5oe18qavsqbG7xM+0F71TGs= X-Google-Smtp-Source: AA0mqf4z4SYFPiHOJjNUF3LZrUpSaAlelX76L5wpv4K+CvQMa6/kkCmtm9p734adLuFbG8Uzk8gTJijzbQMhmmDAmOs= X-Received: by 2002:a25:d03:0:b0:6d8:b601:ee51 with SMTP id 3-20020a250d03000000b006d8b601ee51mr194880ybn.60.1667813433382; Mon, 07 Nov 2022 01:30:33 -0800 (PST) MIME-Version: 1.0 References: <20221106125651.501400-1-lingling.kong@intel.com> In-Reply-To: From: Uros Bizjak Date: Mon, 7 Nov 2022 10:30:22 +0100 Message-ID: Subject: Re: [PATCH] i386: Prefer remote atomic insn for atomic_fetch{add, and, or, xor} To: "Kong, Lingling" Cc: "Liu, Hongtao" , "gcc-patches@gcc.gnu.org" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Sun, Nov 6, 2022 at 2:00 PM Kong, Lingling via Gcc-patches wrote: > > Hi > > The patch is to add flag -mprefer-remote-atomic to control whether to generate raoint insn for atomic operations. > Ok for trunk? Please note TARGET_AVOID_MFENCE tuning flag, introduced a while ago due to the fact that several targets perform LOCK OR faster than MFENCE. It was determined that MFENCE/SFENCE/LFENCE are much more complex instructions compared to LOCK OR, since they have to handle cases that C memory model never describes (some MMIO, or such). Considering that ordinary LOCKed operations adequately cover C memory model, and are probably faster than new instructions that have to cover all special cases, I wonder if there is really benefit to emit these insns instead of existing LOCKed operations. These should IMO be used only via relevant builtins. Uros. > > BRs, > Lingling > > gcc/ChangeLog: > > * config/i386/i386.opt:Add -mprefer-remote-atomic. > * config/i386/sync.md (atomic_): > New define_expand. > (atomic_add): Rename to below one. > (atomic_add_1): To this. > (atomic_): Ditto. > (atomic__1): Ditto. > > gcc/testsuite/ChangeLog: > > * gcc.target/i386/raoint-atomic-fetch.c: New test. > --- > gcc/config/i386/i386.opt | 4 +++ > gcc/config/i386/sync.md | 29 ++++++++++++++++--- > .../gcc.target/i386/raoint-atomic-fetch.c | 29 +++++++++++++++++++ > 3 files changed, 58 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/raoint-atomic-fetch.c > > diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index 415c52e1bb4..abb1e5ecbdc 100644 > --- a/gcc/config/i386/i386.opt > +++ b/gcc/config/i386/i386.opt > @@ -1246,3 +1246,7 @@ Support PREFETCHI built-in functions and code generation. > mraoint > Target Mask(ISA2_RAOINT) Var(ix86_isa_flags2) Save Support RAOINT built-in functions and code generation. > + > +mprefer-remote-atomic > +Target Var(flag_prefer_remote_atomic) Init(0) Prefer use remote atomic > +insn for atomic operations. > diff --git a/gcc/config/i386/sync.md b/gcc/config/i386/sync.md index e6543a5efb0..08e944fc9b7 100644 > --- a/gcc/config/i386/sync.md > +++ b/gcc/config/i386/sync.md > @@ -37,7 +37,7 @@ > UNSPECV_CMPXCHG > UNSPECV_XCHG > UNSPECV_LOCK > - > + > ;; For CMPccXADD support > UNSPECV_CMPCCXADD > > @@ -791,7 +791,28 @@ > (define_code_iterator any_plus_logic [and ior xor plus]) (define_code_attr plus_logic [(and "and") (ior "or") (xor "xor") (plus "add")]) > > -(define_insn "rao_a" > +(define_expand "atomic_" > + [(match_operand:SWI 0 "memory_operand") > + (any_plus_logic:SWI (match_dup 0) > + (match_operand:SWI 1 "nonmemory_operand")) > + (match_operand:SI 2 "const_int_operand")] > + "" > +{ > + if (flag_prefer_remote_atomic > + && TARGET_RAOINT && operands[2] == const0_rtx > + && (mode == SImode || mode == DImode)) > + { > + if (CONST_INT_P (operands[1])) > + operands[1] = force_reg (mode, operands[1]); > + emit_insn (maybe_gen_rao_a (, mode, operands[0], > +operands[1])); > + } > + else > + emit_insn (gen_atomic__1 (operands[0], operands[1], > + operands[2])); > + DONE; > +}) > + > +(define_insn "@rao_a" > [(set (match_operand:SWI48 0 "memory_operand" "+m") > (unspec_volatile:SWI48 > [(any_plus_logic:SWI48 (match_dup 0) @@ -801,7 +822,7 @@ > "TARGET_RAOINT" > "a\t{%1, %0|%0, %1}") > > -(define_insn "atomic_add" > +(define_insn "atomic_add_1" > [(set (match_operand:SWI 0 "memory_operand" "+m") > (unspec_volatile:SWI > [(plus:SWI (match_dup 0) > @@ -855,7 +876,7 @@ > return "lock{%;} %K2sub{}\t{%1, %0|%0, %1}"; > }) > > -(define_insn "atomic_" > +(define_insn "atomic__1" > [(set (match_operand:SWI 0 "memory_operand" "+m") > (unspec_volatile:SWI > [(any_logic:SWI (match_dup 0) > diff --git a/gcc/testsuite/gcc.target/i386/raoint-atomic-fetch.c b/gcc/testsuite/gcc.target/i386/raoint-atomic-fetch.c > new file mode 100644 > index 00000000000..ac4099d888e > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/raoint-atomic-fetch.c > @@ -0,0 +1,29 @@ > +/* { dg-do compile } */ > +/* { dg-options "-mraoint -O2 -mprefer-remote-atomic" } */ > +/* { dg-final { scan-assembler-times "aadd" 2 { target {! ia32 } } } } > +*/ > +/* { dg-final { scan-assembler-times "aand" 2 { target {! ia32 } } } } > +*/ > +/* { dg-final { scan-assembler-times "aor" 2 { target {! ia32 } } } } > +*/ > +/* { dg-final { scan-assembler-times "axor" 2 { target {! ia32 } } } } > +*/ > +/* { dg-final { scan-assembler-times "aadd" 1 { target ia32 } } } */ > +/* { dg-final { scan-assembler-times "aand" 1 { target ia32 } } } */ > +/* { dg-final { scan-assembler-times "aor" 1 { target ia32 } } } */ > +/* { dg-final { scan-assembler-times "axor" 1 { target ia32 } } } */ > +volatile int x; volatile long long y; int *a; long long *b; > + > +void extern > +rao_int_test (void) > +{ > + __atomic_add_fetch (a, x, __ATOMIC_RELAXED); > + __atomic_and_fetch (a, x, __ATOMIC_RELAXED); > + __atomic_or_fetch (a, x, __ATOMIC_RELAXED); > + __atomic_xor_fetch (a, x, __ATOMIC_RELAXED); #ifdef __x86_64__ > + __atomic_add_fetch (b, y, __ATOMIC_RELAXED); > + __atomic_and_fetch (b, y, __ATOMIC_RELAXED); > + __atomic_or_fetch (b, y, __ATOMIC_RELAXED); > + __atomic_xor_fetch (b, y, __ATOMIC_RELAXED); #endif } > -- > 2.27.0 >