From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw1-x1130.google.com (mail-yw1-x1130.google.com [IPv6:2607:f8b0:4864:20::1130]) by sourceware.org (Postfix) with ESMTPS id E56C53857BA4 for ; Mon, 14 Nov 2022 07:55:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E56C53857BA4 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-yw1-x1130.google.com with SMTP id 00721157ae682-381662c78a9so17726537b3.7 for ; Sun, 13 Nov 2022 23:55:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=9bGiv/miyshMif24ro7hy2x6aQo2YPnD8Sc+iwNl05E=; b=jrX99/hWz4f5AiaGs8HszAuCwIBipf15V4jcqUsue8oLELtrUX9XQXCY4yBIKAjTqa J/AuxCpE0sEKXUlnutq2gvn9nU/W339BBJpWg2QhIBTZqiIESUm2oo+skdiBXHDj84iR iiSgdjCas2ZMrYsTKD/A9WGNJSxnPH5rk2TdZ+jYO+fBqW2EVZzPlzt6qjh1BqYnMRks mT6D3oUFIeOgW+tMTjby7X0n9db8lX1EmDcpC94mB6ATVZT7tuP6zZjaJPmURvqN9pzj NkrmFpyKjfrDsFuV5xQjkGrLYl4Brmq2qD/oqgTI92PTr8m2cNDWXpo+ZS2S31tTuo+6 nzkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=9bGiv/miyshMif24ro7hy2x6aQo2YPnD8Sc+iwNl05E=; b=RMbBo/6hN2bJdR4jvr1WOz/y6r4HH6zSU+vscYfi59DkESgwoL42PuQLcY0Pw4HSjU ZClaN0x4trjeGDbtTSkAK37J1TbFO4YZtm/x2iYJvo5PWPUk1NAbP1TMy7lZ4+PzLQlj MFcv2OVwmPRxYOmYEH+DYLuv4vs3MdvABVc6dHNnFYbQn3NlYIAW68U2iICvNi652ovp W6tEQWgnOZQZKvQBMmescH7BVBGfwjLDmFNOa+B9PaDO/noKUQEA15iag//JrX+361wV kCM24Yw2e0Ut/MWvI3/6UezM3ehXLLUC+oDMZIwFM12cCQU2fDjhHjglemmtovxJyx8X j9rQ== X-Gm-Message-State: ANoB5pnkIImeRqDrmPZox7GoOo6SGH+NxD9Tw0ZBw2D24jk/OutoJJ5w b9wi3sJwBsPCP4vnq65M4hkcJbhGylAsR+Nc54o= X-Google-Smtp-Source: AA0mqf4ao/5ckLKwEFsDWC04kpK1yO7PGZtYtU4RtYnIvroT8zZu+SNGMrTS6ckYUyY5fnlwNWok0vkLSy4pcBMMgqo= X-Received: by 2002:a81:4c10:0:b0:360:7f0a:1620 with SMTP id z16-20020a814c10000000b003607f0a1620mr11848212ywa.192.1668412523278; Sun, 13 Nov 2022 23:55:23 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Uros Bizjak Date: Mon, 14 Nov 2022 08:55:11 +0100 Message-ID: Subject: Re: [PATCH] libatomic: Handle AVX+CX16 AMD like Intel for 16b atomics [PR104688] To: Jakub Jelinek Cc: Richard Biener , Jeff Law , gcc-patches@gcc.gnu.org, Florian Weimer , "H.J. Lu" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-2.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, Nov 14, 2022 at 8:48 AM Jakub Jelinek wrote: > > Hi! > > Working virtually out of Baker Island. > > We got a response from AMD in > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688#c10 > so the following patch starts treating AMD with AVX and CMPXCHG16B > ISAs like Intel by using vmovdqa for atomic load/store in libatomic. > > Ok for trunk if it passes bootstrap/regtest? > > 2022-11-13 Jakub Jelinek > > PR target/104688 > * config/x86/init.c (__libat_feat1_init): Revert 2022-03-17 change > - on x86_64 no longer clear bit_AVX if CPU vendor is not Intel. > > --- libatomic/config/x86/init.c.jj 2022-03-17 18:48:56.708723194 +0100 > +++ libatomic/config/x86/init.c 2022-11-13 18:23:26.315440071 -1200 > @@ -34,18 +34,6 @@ __libat_feat1_init (void) > unsigned int eax, ebx, ecx, edx; > FEAT1_REGISTER = 0; > __get_cpuid (1, &eax, &ebx, &ecx, &edx); > -#ifdef __x86_64__ > - if ((FEAT1_REGISTER & (bit_AVX | bit_CMPXCHG16B)) > - == (bit_AVX | bit_CMPXCHG16B)) > - { > - /* Intel SDM guarantees that 16-byte VMOVDQA on 16-byte aligned address > - is atomic, but so far we don't have this guarantee from AMD. */ > - unsigned int ecx2 = 0; > - __get_cpuid (0, &eax, &ebx, &ecx2, &edx); > - if (ecx2 != signature_INTEL_ecx) > - FEAT1_REGISTER &= ~bit_AVX; We still need this, but also bypass it for AMD signature. There are other vendors than Intel and AMD. OK with the above addition. Thanks, Uros. > - } > -#endif > /* See the load in load_feat1. */ > __atomic_store_n (&__libat_feat1, FEAT1_REGISTER, __ATOMIC_RELAXED); > return FEAT1_REGISTER; > > Jakub >