From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qt1-x834.google.com (mail-qt1-x834.google.com [IPv6:2607:f8b0:4864:20::834]) by sourceware.org (Postfix) with ESMTPS id 04F01393CC12 for ; Fri, 30 Jul 2021 10:02:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 04F01393CC12 Received: by mail-qt1-x834.google.com with SMTP id h27so5985074qtu.9 for ; Fri, 30 Jul 2021 03:02:54 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Sbta40RKyoQhImf9b8/6nstfO2qJXoMBL2yCDA7Swz0=; b=nFfznGB3vEFnw4D02pmBbGjYpIvvIc1G/pWjc8n5+X4JuEmk6qK26YUGcEd0K3cKTc UDE23t83qZz+vLkeu5kINs2GMKseNgkclw0qu3QmbSuwmClFwiOxVaOychxhYZ1xHTYa puLCiRbXI5jl79fLaimDc6a++RAXWvWd4thZcp/Lv+QXYAPC6G5oTkJeljfoOOVJqQe3 GVEcBEVdC11eLDr/wQ/iYaJWfRn1k2UOL+RSA2VHJeR4vf2yYbxoyvRJxm4IZbogBl8B TaobtCwi3ojBix/BjgwJpV+eaQGRDpLGqRunW2GkDVEbb0tp4GoEONTIcfougobYoMUz +kig== X-Gm-Message-State: AOAM530Psv6YC1U9OgQEDzflHzKV9pEHurTz9IcSev23h8ohgdxejNCB Q9f1TkCmF/nKvvXN/CFiS5d2Ej9eMBXp6oquW0A= X-Google-Smtp-Source: ABdhPJwvTXL1hYPKZ6sYUxP277vgm7nuMJMOQLWjLFDKsWYuGB1zD8t95hriVgoQxHCqHPlxU1H3KCiiASH0VhURXag= X-Received: by 2002:ac8:5552:: with SMTP id o18mr1560133qtr.51.1627639374491; Fri, 30 Jul 2021 03:02:54 -0700 (PDT) MIME-Version: 1.0 References: <20210624121213.3469943-1-hjl.tools@gmail.com> In-Reply-To: From: Uros Bizjak Date: Fri, 30 Jul 2021 12:02:43 +0200 Message-ID: Subject: Re: PING^1 [PATCH v2] x86: Check AVX512 without mask instructions To: Hongtao Liu Cc: "H.J. Lu" , Hongtao Liu , "gcc-patches@gcc.gnu.org" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 30 Jul 2021 10:02:56 -0000 On Mon, Jul 26, 2021 at 5:33 AM Hongtao Liu wrote: > > On Wed, Jul 14, 2021 at 8:27 PM H.J. Lu wrote: > > > > On Fri, Jun 25, 2021 at 5:39 AM H.J. Lu wrote: > > > > > > On Fri, Jun 25, 2021 at 12:50 AM Uros Bizjak wrote: > > > > > > > > On Fri, Jun 25, 2021 at 4:51 AM Hongtao Liu wrote: > > > > > > > > > > On Fri, Jun 25, 2021 at 12:13 AM Uros Bizjak via Gcc-patches > > > > > wrote: > > > > > > > > > > > > On Thu, Jun 24, 2021 at 2:12 PM H.J. Lu wrote: > > > > > > > > > > > > > > CPUID functions are used to detect CPU features. If vector ISAs > > > > > > > are enabled, compiler is free to use them in these functions. Add > > > > > > > __attribute__ ((target("general-regs-only"))) to CPUID functions > > > > > > > to avoid vector instructions. > > > > > > > > > > > > These functions are intended to be inlined, so how does target > > > > > > attribute affect inlining? > > > > > I guess w/ -O0. they may not be inlined, that's why H.J adds those > > > > > attributes to those functions. > > > > > > > > The problem is not with these functions, but with surrounding checks > > > > for cpuid features. These checks are implemented with logic > > > > instructions, and nothing prevents RA from allocating mask registers, > > > > and consequently mask insn is emitted. Regarding mentioned functions, > > > > cpuid insn pattern has four GPR single-reg constraints, so mask > > > > registers can't be allocated here. > > > > > > > > > pr96814.dump: > > > > > 0804aa40
: > > > > > 804aa40: 8d 4c 24 04 lea 0x4(%esp),%ecx > > > > > ... > > > > > 804aa63: 6a 07 push $0x7 > > > > > 804aa65: e8 e0 e7 ff ff call 804924a <__get_cpuid_count> > > > > > > > > > > Also we need to add a target attribute to avx512f_os_support (), and > > > > > that would be enough to fix the AVX512 part. > > > > > > > > > > Moreover, all check functions in below files may also need to deal with: > > > > > adx-check.h > > > > > aes-avx-check.h > > > > > aes-check.h > > > > > amx-check.h > > > > > attr-nocf-check-1a.c > > > > > attr-nocf-check-3a.c > > > > > avx2-check.h > > > > > avx2-vpop-check.h > > > > > avx512bw-check.h > > > > > avx512-check.h > > > > > avx512dq-check.h > > > > > avx512er-check.h > > > > > avx512f-check.h > > > > > avx512vl-check.h > > > > > avx-check.h > > > > > bmi2-check.h > > > > > bmi-check.h > > > > > cf_check-1.c > > > > > cf_check-2.c > > > > > cf_check-3.c > > > > > cf_check-4.c > > > > > cf_check-5.c > > > > > f16c-check.h > > > > > fma4-check.h > > > > > fma-check.h > > > > > isa-check.h > > > > > lzcnt-check.h > > > > > m128-check.h > > > > > m256-check.h > > > > > m512-check.h > > > > > mmx-3dnow-check.h > > > > > mmx-check.h > > > > > pclmul-avx-check.h > > > > > pclmul-check.h > > > > > pr39315-check.c > > > > > rtm-check.h > > > > > sha-check.h > > > > > spellcheck-options-1.c > > > > > spellcheck-options-2.c > > > > > spellcheck-options-3.c > > > > > spellcheck-options-4.c > > > > > spellcheck-options-5.c > > > > > sse2-check.h > > > > > sse3-check.h > > > > > sse4_1-check.h > > > > > sse4_2-check.h > > > > > sse4a-check.h > > > > > sse-check.h > > > > > ssse3-check.h > > > > > stack-check-11.c > > > > > stack-check-12.c > > > > > stack-check-17.c > > > > > stack-check-18.c > > > > > stack-check-19.c > > > > > xop-check.h > > > > > > > > True, but this would just paper over the real problem. Now, it is > > > > expected that the user decorates the function that checks CPUID > > > > features with the target attribute. I'm not sure if this is OK. > vmovw is enabled by AVX512FP16, and compile cpuid check function w/ > avx512fp16 may result in SIGILL on non-avx512fp16 target(though, we > didn't get a testcase yet). In struct processor_costs (i386.h) we have: const int sse_to_integer; /* cost of moving SSE register to integer. */ const int integer_to_sse; /* cost of moving integer register to SSE. */ const int mask_to_integer; /* cost of moving mask register to integer. */ const int integer_to_mask; /* cost of moving integer register to mask. */ These are currently set sufficiently high, so we won't get vmovw for the same reason we don't get vmovd and vmovq. > Would that be a sufficient reason to disable avx512 for cpuid check? We would like to avoid inter-unit moves, and keep values in their respective register set as much as possible. This is the reason for relatively high values for the above costs and special passes were introduced (STV) to avoid excessive moves between register sets. Without this approach, register allocator is free to generate e.g. instructions with mask registers instead of integer registers (especially under register pressure), trading spills with inter-unit moves. We tried to spill to SSE registers, and the experiment ended with a nice list of PRs. See ix86_spill_class in i386.c. Decorating the function with general_regs_only would just paper over the above problem. Regarding mask registers, some sort of STV-like target pass is needed to control precisely how values are moved between register sets, loaded to mask registers, handled there and stored. Uros.