* [PATCH, i386] Avoid 512-bit vector return constant for Intel AVX512 configuration
@ 2017-09-28 13:08 Shalnov, Sergey
2017-09-28 13:16 ` Uros Bizjak
0 siblings, 1 reply; 4+ messages in thread
From: Shalnov, Sergey @ 2017-09-28 13:08 UTC (permalink / raw)
To: gcc-patches
Cc: ubizjak, kirill.yukhin, Senkevich, Andrew, Ivchenko, Alexander,
Peryt, Sebastian
[-- Attachment #1: Type: text/plain, Size: 414 bytes --]
Hi,
GCC uses full 512-bit register to return the constant from the function.
The patch avoid 512-bit register usage if "-mprefer-avx256" option used.
2017-09-28 Sergey Shalnov <Sergey.Shalnov@intel.com>
gcc/
* config/i386/i386.md(*movsf_internal, *movdf_internal):
Return 256-bit AVX modes for TARGET_PREFER_AVX256.
gcc/testsuite/
* gcc.target/i386/avx512f-constant-float-return.c: New test.
[-- Attachment #2: 0001-Avoid-useing-zmm-if-TARGET_PREFER_AVX256.patch --]
[-- Type: application/octet-stream, Size: 1818 bytes --]
From b1ad8c14cded34ec1829b7f2427c2737f0a74723 Mon Sep 17 00:00:00 2001
From: Sergey Shalnov <Sergey.Shalnov@intel.com>
Date: Fri, 22 Sep 2017 12:43:11 +0300
Subject: [PATCH 1/1] Avoid useing zmm if TARGET_PREFER_AVX256
---
gcc/config/i386/i386.md | 4 ++--
.../gcc.target/i386/avx512f-constant-float-return.c | 15 +++++++++++++++
2 files changed, 17 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-constant-float-return.c
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index f51e02c..db48cc0 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -3524,7 +3524,7 @@
(eq_attr "alternative" "12,16")
(cond [(not (match_test "TARGET_SSE2"))
(const_string "V4SF")
- (match_test "TARGET_AVX512F")
+ (match_test "TARGET_AVX512F && !TARGET_PREFER_AVX256")
(const_string "XI")
(match_test "TARGET_AVX")
(const_string "V2DF")
@@ -3693,7 +3693,7 @@
(eq_attr "alternative" "5")
(cond [(not (match_test "TARGET_SSE2"))
(const_string "V4SF")
- (match_test "TARGET_AVX512F")
+ (match_test "TARGET_AVX512F && !TARGET_PREFER_AVX256")
(const_string "V16SF")
(match_test "TARGET_AVX")
(const_string "V4SF")
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-constant-float-return.c b/gcc/testsuite/gcc.target/i386/avx512f-constant-float-return.c
new file mode 100644
index 0000000..153cf69
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-constant-float-return.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -march=skylake-avx512 -mprefer-avx256" } */
+/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */
+
+float
+my_test_f()
+{
+ return 0.0f;
+}
+
+double
+my_test_d()
+{
+ return 0.0;
+}
--
1.8.3.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH, i386] Avoid 512-bit vector return constant for Intel AVX512 configuration
2017-09-28 13:08 [PATCH, i386] Avoid 512-bit vector return constant for Intel AVX512 configuration Shalnov, Sergey
@ 2017-09-28 13:16 ` Uros Bizjak
2017-09-28 14:05 ` Shalnov, Sergey
0 siblings, 1 reply; 4+ messages in thread
From: Uros Bizjak @ 2017-09-28 13:16 UTC (permalink / raw)
To: Shalnov, Sergey
Cc: gcc-patches, kirill.yukhin, Senkevich, Andrew, Ivchenko,
Alexander, Peryt, Sebastian
On Thu, Sep 28, 2017 at 3:08 PM, Shalnov, Sergey
<sergey.shalnov@intel.com> wrote:
> Hi,
> GCC uses full 512-bit register to return the constant from the function.
> The patch avoid 512-bit register usage if "-mprefer-avx256" option used.
>
> 2017-09-28 Sergey Shalnov <Sergey.Shalnov@intel.com>
>
> gcc/
> * config/i386/i386.md(*movsf_internal, *movdf_internal):
> Return 256-bit AVX modes for TARGET_PREFER_AVX256.
>
> gcc/testsuite/
> * gcc.target/i386/avx512f-constant-float-return.c: New test.
>
- (match_test "TARGET_AVX512F")
+ (match_test "TARGET_AVX512F && !TARGET_PREFER_AVX256")
Please use
(and (match_test "TARGET_AVX512F)
(not (match_test "TARGET_PREFER_AVX256)))
Uros.
^ permalink raw reply [flat|nested] 4+ messages in thread
* RE: [PATCH, i386] Avoid 512-bit vector return constant for Intel AVX512 configuration
2017-09-28 13:16 ` Uros Bizjak
@ 2017-09-28 14:05 ` Shalnov, Sergey
2017-09-28 18:12 ` Uros Bizjak
0 siblings, 1 reply; 4+ messages in thread
From: Shalnov, Sergey @ 2017-09-28 14:05 UTC (permalink / raw)
To: Uros Bizjak
Cc: gcc-patches, kirill.yukhin, Senkevich, Andrew, Ivchenko,
Alexander, Peryt, Sebastian
[-- Attachment #1: Type: text/plain, Size: 1284 bytes --]
Sorry. The patch is changed as you proposed.
-----Original Message-----
From: Uros Bizjak [mailto:ubizjak@gmail.com]
Sent: Thursday, September 28, 2017 3:17 PM
To: Shalnov, Sergey <sergey.shalnov@intel.com>
Cc: gcc-patches@gcc.gnu.org; kirill.yukhin@gmail.com; Senkevich, Andrew <andrew.senkevich@intel.com>; Ivchenko, Alexander <alexander.ivchenko@intel.com>; Peryt, Sebastian <sebastian.peryt@intel.com>
Subject: Re: [PATCH, i386] Avoid 512-bit vector return constant for Intel AVX512 configuration
On Thu, Sep 28, 2017 at 3:08 PM, Shalnov, Sergey <sergey.shalnov@intel.com> wrote:
> Hi,
> GCC uses full 512-bit register to return the constant from the function.
> The patch avoid 512-bit register usage if "-mprefer-avx256" option used.
>
> 2017-09-28 Sergey Shalnov <Sergey.Shalnov@intel.com>
>
> gcc/
> * config/i386/i386.md(*movsf_internal, *movdf_internal):
> Return 256-bit AVX modes for TARGET_PREFER_AVX256.
>
> gcc/testsuite/
> * gcc.target/i386/avx512f-constant-float-return.c: New test.
>
- (match_test "TARGET_AVX512F")
+ (match_test "TARGET_AVX512F && !TARGET_PREFER_AVX256")
Please use
(and (match_test "TARGET_AVX512F)
(not (match_test "TARGET_PREFER_AVX256)))
Uros.
[-- Attachment #2: 0001-Avoid-useing-zmm-if-TARGET_PREFER_AVX256.patch --]
[-- Type: application/octet-stream, Size: 1878 bytes --]
From 07327a8871d8e8eec1f33be31ea0bfdc0596ddd8 Mon Sep 17 00:00:00 2001
From: Sergey Shalnov <Sergey.Shalnov@intel.com>
Date: Fri, 22 Sep 2017 12:43:11 +0300
Subject: [PATCH 1/1] Avoid useing zmm if TARGET_PREFER_AVX256
---
gcc/config/i386/i386.md | 6 ++++--
.../gcc.target/i386/avx512f-constant-float-return.c | 15 +++++++++++++++
2 files changed, 19 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-constant-float-return.c
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index f51e02c..b9a3928 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -3524,7 +3524,8 @@
(eq_attr "alternative" "12,16")
(cond [(not (match_test "TARGET_SSE2"))
(const_string "V4SF")
- (match_test "TARGET_AVX512F")
+ (and (match_test "TARGET_AVX512F")
+ (not (match_test "TARGET_PREFER_AVX256")))
(const_string "XI")
(match_test "TARGET_AVX")
(const_string "V2DF")
@@ -3693,7 +3694,8 @@
(eq_attr "alternative" "5")
(cond [(not (match_test "TARGET_SSE2"))
(const_string "V4SF")
- (match_test "TARGET_AVX512F")
+ (and (match_test "TARGET_AVX512F")
+ (not (match_test "TARGET_PREFER_AVX256")))
(const_string "V16SF")
(match_test "TARGET_AVX")
(const_string "V4SF")
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-constant-float-return.c b/gcc/testsuite/gcc.target/i386/avx512f-constant-float-return.c
new file mode 100644
index 0000000..153cf69
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-constant-float-return.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -march=skylake-avx512 -mprefer-avx256" } */
+/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */
+
+float
+my_test_f()
+{
+ return 0.0f;
+}
+
+double
+my_test_d()
+{
+ return 0.0;
+}
--
1.8.3.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH, i386] Avoid 512-bit vector return constant for Intel AVX512 configuration
2017-09-28 14:05 ` Shalnov, Sergey
@ 2017-09-28 18:12 ` Uros Bizjak
0 siblings, 0 replies; 4+ messages in thread
From: Uros Bizjak @ 2017-09-28 18:12 UTC (permalink / raw)
To: Shalnov, Sergey
Cc: gcc-patches, kirill.yukhin, Senkevich, Andrew, Ivchenko,
Alexander, Peryt, Sebastian
On Thu, Sep 28, 2017 at 4:05 PM, Shalnov, Sergey
<sergey.shalnov@intel.com> wrote:
> Sorry. The patch is changed as you proposed.
OK for mainline and committed.
Thanks,
Uros.
> -----Original Message-----
> From: Uros Bizjak [mailto:ubizjak@gmail.com]
> Sent: Thursday, September 28, 2017 3:17 PM
> To: Shalnov, Sergey <sergey.shalnov@intel.com>
> Cc: gcc-patches@gcc.gnu.org; kirill.yukhin@gmail.com; Senkevich, Andrew <andrew.senkevich@intel.com>; Ivchenko, Alexander <alexander.ivchenko@intel.com>; Peryt, Sebastian <sebastian.peryt@intel.com>
> Subject: Re: [PATCH, i386] Avoid 512-bit vector return constant for Intel AVX512 configuration
>
> On Thu, Sep 28, 2017 at 3:08 PM, Shalnov, Sergey <sergey.shalnov@intel.com> wrote:
>> Hi,
>> GCC uses full 512-bit register to return the constant from the function.
>> The patch avoid 512-bit register usage if "-mprefer-avx256" option used.
>>
>> 2017-09-28 Sergey Shalnov <Sergey.Shalnov@intel.com>
>>
>> gcc/
>> * config/i386/i386.md(*movsf_internal, *movdf_internal):
>> Return 256-bit AVX modes for TARGET_PREFER_AVX256.
>>
>> gcc/testsuite/
>> * gcc.target/i386/avx512f-constant-float-return.c: New test.
>>
>
> - (match_test "TARGET_AVX512F")
> + (match_test "TARGET_AVX512F && !TARGET_PREFER_AVX256")
>
> Please use
>
> (and (match_test "TARGET_AVX512F)
> (not (match_test "TARGET_PREFER_AVX256)))
>
> Uros.
^ permalink raw reply [flat|nested] 4+ messages in thread
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2017-09-28 13:08 [PATCH, i386] Avoid 512-bit vector return constant for Intel AVX512 configuration Shalnov, Sergey
2017-09-28 13:16 ` Uros Bizjak
2017-09-28 14:05 ` Shalnov, Sergey
2017-09-28 18:12 ` Uros Bizjak
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