From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 38509 invoked by alias); 9 Jul 2015 20:13:54 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 38500 invoked by uid 89); 9 Jul 2015 20:13:53 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.8 required=5.0 tests=AWL,BAYES_50,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-ob0-f176.google.com Received: from mail-ob0-f176.google.com (HELO mail-ob0-f176.google.com) (209.85.214.176) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Thu, 09 Jul 2015 20:13:52 +0000 Received: by obbkm3 with SMTP id km3so178602260obb.1 for ; Thu, 09 Jul 2015 13:13:50 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.202.240.215 with SMTP id o206mr15367554oih.94.1436472830043; Thu, 09 Jul 2015 13:13:50 -0700 (PDT) Received: by 10.60.147.170 with HTTP; Thu, 9 Jul 2015 13:13:49 -0700 (PDT) In-Reply-To: <20150709193808.GA10247@tucnak.redhat.com> References: <20150709193808.GA10247@tucnak.redhat.com> Date: Thu, 09 Jul 2015 20:13:00 -0000 Message-ID: Subject: Re: [PATCH, i386]: Fix PR 66814, ICE: gcc.target/i386/avx512f-klogic-2.c From: Uros Bizjak To: Jakub Jelinek Cc: "gcc-patches@gcc.gnu.org" Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SW-Source: 2015-07/txt/msg00816.txt.bz2 On Thu, Jul 9, 2015 at 9:38 PM, Jakub Jelinek wrote: > On Thu, Jul 09, 2015 at 05:22:33PM +0200, Uros Bizjak wrote: >> Hello! >> >> This ICE was caused by a peephole2 pattern that allowed non-general >> regs arguments. >> >> 2015-07-08 Uros Bizjak >> >> PR target/66814 >> * config/i386/predicates.md (nonimmediate_gr_operand): New predicate. >> * config/i386/i386.md (not peephole2): Use nonimmediate_gr_operand. >> (varous peephole2s): Use {GENERAL,SSE,MMX}_REGNO_P instead of >> {GENERAL_SSE_MMX}_REG_P where appropriate. > > This patch breaks bootstrap with rtl checking on x86_64-linux. > > ../../gcc/tree-vect-loop.c: In function =E2=80=98void calc_vec_perm_mask_= for_shift(machine_mode, unsigned int, unsigned char*)=E2=80=99: > ../../gcc/tree-vect-loop.c:3190:1: internal compiler error: RTL check: ex= pected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1782 > } > ^ > 0x11a44ef rtl_check_failed_code1(rtx_def const*, rtx_code, char const*, i= nt, char const*) > ../../gcc/rtl.c:786 > 0x19e917c rhs_regno > ../../gcc/rtl.h:1782 > 0x1d20eea peephole2_10 > ../../gcc/config/i386/i386.md:17699 > 0x1d2ccc8 peephole2_insns(rtx_def*, rtx_insn*, int*) > ../../gcc/config/i386/i386.md:5050 > 0x11190e0 peephole2_optimize > ../../gcc/recog.c:3627 > 0x111a81f rest_of_handle_peephole2 > ../../gcc/recog.c:3807 > 0x111a8d4 execute > ../../gcc/recog.c:3841 > > register_operand allows a SUBREG even after a reload, as long as > it is a SUBREG of a REG_P. > > insn in question is: > (insn 75 71 76 2 (set (subreg:SI (reg:DI 2 cx) 0) > (const_int -1 [0xffffffffffffffff])) ../../gcc/tree-vect-loop.c:3= 189 -1 > (nil)) > > and has been created by the: > ;; After splitting up read-modify operations, array accesses with memory > ;; operands might end up in form: > ;; sall $2, %eax > ;; movl 4(%esp), %edx > ;; addl %edx, %eax > ;; instead of pre-splitting: > ;; sall $2, %eax > ;; addl 4(%esp), %eax > ;; Turn it into: > ;; movl 4(%esp), %edx > ;; leal (%edx,%eax,4), %eax > peephole2. > Wonder if > if (mode !=3D word_mode) > operands[1] =3D gen_rtx_SUBREG (mode, operands[1], 0); > if (op1mode !=3D word_mode) > operands[5] =3D gen_rtx_SUBREG (op1mode, operands[5], 0); > should not have been gen_lowpart instead of gen_rtx_SUBREG. > In any case, it wouldn't surprise me if there aren't many other ways > how to get a SUBREG in there. I was under impression that peephole2 pass doesn't see subregs of hard regs (all x86 predicates are written in this way). Even documentation somehow agrees with this: '(subreg:M1 REG:M2 BYTENUM)' 'subreg' expressions are used to refer to a register in a machine mode other than its natural one, or to refer to one register of a multi-part 'reg' that actually refers to several registers. Each pseudo register has a natural mode. If it is necessary to operate on it in a different mode, the register must be enclosed in a 'subreg'. There are currently three supported types for the first operand of a 'subreg': [...] * hard registers It is seldom necessary to wrap hard registers in 'subreg's; such registers would normally reduce to a single 'reg' rtx. This use of 'subreg's is discouraged and may not be supported in the future. So, I'd say that generating naked SUBREG after reload should be avoided and gen_lowpart should be used in the code above. Uros. > Jakub