From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 25909 invoked by alias); 14 Feb 2019 14:04:19 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 25513 invoked by uid 89); 14 Feb 2019 14:04:19 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00,FREEMAIL_FROM,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-it1-f196.google.com Received: from mail-it1-f196.google.com (HELO mail-it1-f196.google.com) (209.85.166.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 14 Feb 2019 14:04:16 +0000 Received: by mail-it1-f196.google.com with SMTP id v72so14629256itc.0 for ; Thu, 14 Feb 2019 06:04:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=LYAuzzErcMCru2D7fmBjs4GEgR+NyFma4N0/djPuZ9Y=; b=dQv0WumM5Si4ZjM9x0minxTfBQcPYEJA/WQnL6RIxoOe84fvKnYryTH7bIuDBBvBha F1lzoymauEoDm6ztxMJJheNuscdeKlIe2wps8ohAnS9gF0KaTKp30IEQ5SrTQ4yyaZPP f7f16yExe+3OfM+4Jqzc3/0cp2B8t+dUa6lGWWASPsh1+OYLKIFirngA7sf9QLYvLR0j KsBJvWJzOQf6sdeD/sC0AHJAsLRBgtitv5XiJsJEiPib+VEl86jx9nFoJAHfkHgyhU6R GZNhSBUjSbtQjZHWWAEMwpvS5NIID8v/0FwcPj+Lv0i1BaO9CXl8d3d2dSorQqDEGkLg hCdA== MIME-Version: 1.0 References: <20190214123031.13301-1-hjl.tools@gmail.com> <20190214123031.13301-9-hjl.tools@gmail.com> In-Reply-To: <20190214123031.13301-9-hjl.tools@gmail.com> From: Uros Bizjak Date: Thu, 14 Feb 2019 14:04:00 -0000 Message-ID: Subject: Re: [PATCH 08/40] i386: Emulate MMX ashr3/3 with SSE To: "H.J. Lu" Cc: "gcc-patches@gcc.gnu.org" Content-Type: text/plain; charset="UTF-8" X-SW-Source: 2019-02/txt/msg01074.txt.bz2 On Thu, Feb 14, 2019 at 1:30 PM H.J. Lu wrote: > > Emulate MMX ashr3/3 with SSE. Only SSE register > source operand is allowed. > > PR target/89021 > * config/i386/mmx.md (mmx_ashr3): Changed to define_expand. > Disallow TARGET_MMX_WITH_SSE. > (mmx_3): Likewise. > (ashr3): New. > (*ashr3): Likewise. > (3): Likewise. > (*3): Likewise. Please add "|| TARGET_MMX_WITH_SSE" with new constraints to mmx_*3 insn instead and don't introduce unnecessary mmx_* expander. Uros. > --- > gcc/config/i386/mmx.md | 68 ++++++++++++++++++++++++++++++++---------- > 1 file changed, 52 insertions(+), 16 deletions(-) > > diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md > index 23c10dffc38..4738d6b428e 100644 > --- a/gcc/config/i386/mmx.md > +++ b/gcc/config/i386/mmx.md > @@ -958,33 +958,69 @@ > [(set_attr "type" "mmxadd") > (set_attr "mode" "DI")]) > > -(define_insn "mmx_ashr3" > - [(set (match_operand:MMXMODE24 0 "register_operand" "=y") > +(define_expand "mmx_ashr3" > + [(set (match_operand:MMXMODE24 0 "register_operand") > (ashiftrt:MMXMODE24 > - (match_operand:MMXMODE24 1 "register_operand" "0") > - (match_operand:DI 2 "nonmemory_operand" "yN")))] > - "TARGET_MMX" > - "psra\t{%2, %0|%0, %2}" > - [(set_attr "type" "mmxshft") > + (match_operand:MMXMODE24 1 "register_operand") > + (match_operand:DI 2 "nonmemory_operand")))] > + "TARGET_MMX || TARGET_MMX_WITH_SSE") > + > +(define_expand "ashr3" > + [(set (match_operand:MMXMODE24 0 "register_operand") > + (ashiftrt:MMXMODE24 > + (match_operand:MMXMODE24 1 "register_operand") > + (match_operand:DI 2 "nonmemory_operand")))] > + "TARGET_MMX_WITH_SSE") > + > +(define_insn "*ashr3" > + [(set (match_operand:MMXMODE24 0 "register_operand" "=y,x,Yv") > + (ashiftrt:MMXMODE24 > + (match_operand:MMXMODE24 1 "register_operand" "0,0,Yv") > + (match_operand:DI 2 "nonmemory_operand" "yN,xN,YvN")))] > + "TARGET_MMX || TARGET_MMX_WITH_SSE" > + "@ > + psra\t{%2, %0|%0, %2} > + psra\t{%2, %0|%0, %2} > + vpsra\t{%2, %1, %0|%0, %1, %2}" > + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") > + (set_attr "type" "mmxshft,sseishft,sseishft") > (set (attr "length_immediate") > (if_then_else (match_operand 2 "const_int_operand") > (const_string "1") > (const_string "0"))) > - (set_attr "mode" "DI")]) > + (set_attr "mode" "DI,TI,TI")]) > > -(define_insn "mmx_3" > - [(set (match_operand:MMXMODE248 0 "register_operand" "=y") > +(define_expand "mmx_3" > + [(set (match_operand:MMXMODE248 0 "register_operand") > (any_lshift:MMXMODE248 > - (match_operand:MMXMODE248 1 "register_operand" "0") > - (match_operand:DI 2 "nonmemory_operand" "yN")))] > - "TARGET_MMX" > - "p\t{%2, %0|%0, %2}" > - [(set_attr "type" "mmxshft") > + (match_operand:MMXMODE248 1 "register_operand") > + (match_operand:DI 2 "nonmemory_operand")))] > + "TARGET_MMX || TARGET_MMX_WITH_SSE") > + > +(define_expand "3" > + [(set (match_operand:MMXMODE248 0 "register_operand") > + (any_lshift:MMXMODE248 > + (match_operand:MMXMODE248 1 "register_operand") > + (match_operand:DI 2 "nonmemory_operand")))] > + "TARGET_MMX_WITH_SSE") > + > +(define_insn "*3" > + [(set (match_operand:MMXMODE248 0 "register_operand" "=y,x,Yv") > + (any_lshift:MMXMODE248 > + (match_operand:MMXMODE248 1 "register_operand" "0,0,Yv") > + (match_operand:DI 2 "nonmemory_operand" "yN,xN,YvN")))] > + "TARGET_MMX || TARGET_MMX_WITH_SSE" > + "@ > + p\t{%2, %0|%0, %2} > + p\t{%2, %0|%0, %2} > + vp\t{%2, %1, %0|%0, %1, %2}" > + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") > + (set_attr "type" "mmxshft,sseishft,sseishft") > (set (attr "length_immediate") > (if_then_else (match_operand 2 "const_int_operand") > (const_string "1") > (const_string "0"))) > - (set_attr "mode" "DI")]) > + (set_attr "mode" "DI,TI,TI")]) > > ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; > ;; > -- > 2.20.1 >