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Tue, 05 Dec 2023 03:25:59 -0800 (PST) MIME-Version: 1.0 References: <20231205022948.504790-1-hongyu.wang@intel.com> <20231205022948.504790-6-hongyu.wang@intel.com> In-Reply-To: <20231205022948.504790-6-hongyu.wang@intel.com> From: Uros Bizjak Date: Tue, 5 Dec 2023 12:25:48 +0100 Message-ID: Subject: Re: [PATCH 05/17] [APX NDD] Support APX NDD for adc insns To: Hongyu Wang Cc: gcc-patches@gcc.gnu.org, hongtao.liu@intel.com, Kong Lingling Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Tue, Dec 5, 2023 at 3:29=E2=80=AFAM Hongyu Wang = wrote: > > From: Kong Lingling > > Legacy adc patterns are commonly adopted to TImode add, when extending TI= mode > add to NDD version, operands[0] and operands[1] can be different, so extr= a move > should be emitted if those patterns have optimization when adding const0_= rtx. > > NDD instructions will automatically zero-extend dest register to 64bit, s= o for > zext patterns it can adopt all NDD form that have memory src input. > > gcc/ChangeLog: > > * config/i386/i386.md (*add3_doubleword): Add ndd constraint= s, and > move operands[1] to operands[0] when they are not equal. > (*add3_doubleword_cc_overflow_1): Likewise. > (*add3_doubleword_zext): Add ndd constraints. > (*addv4_doubleword): Likewise. > (*addv4_doubleword_1): Likewise. > (addv4_overflow_1): Likewise. > (*addv4_overflow_2): Likewise. > (@add3_carry): Likewise. > (*add3_carry_0): Likewise. > (*addsi3_carry_zext): Likewise. > (addcarry): Likewise. > (addcarry_0): Likewise. > (*addcarry_1): Likewise. > (*add3_eq): Likewise. > (*add3_ne): Likewise. > (*addsi3_carry_zext_0): Likewise, and use nonimmediate_operand fo= r > operands[1] to accept memory input for NDD alternative. > > gcc/testsuite/ChangeLog: > > * gcc.target/i386/apx-ndd-adc.c: New test. > --- > gcc/config/i386/i386.md | 191 ++++++++++++-------- > gcc/testsuite/gcc.target/i386/apx-ndd-adc.c | 15 ++ > 2 files changed, 134 insertions(+), 72 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/i386/apx-ndd-adc.c > > diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md > index 6b316e698bb..358a3857f89 100644 > --- a/gcc/config/i386/i386.md > +++ b/gcc/config/i386/i386.md > @@ -6291,12 +6291,12 @@ (define_expand "add3" > TARGET_APX_NDD); DONE;") > > (define_insn_and_split "*add3_doubleword" > - [(set (match_operand: 0 "nonimmediate_operand" "=3Dro,r") > + [(set (match_operand: 0 "nonimmediate_operand" "=3Dro,r,r,r") > (plus: > - (match_operand: 1 "nonimmediate_operand" "%0,0") > - (match_operand: 2 "x86_64_hilo_general_operand" "r,o")= )) > + (match_operand: 1 "nonimmediate_operand" "%0,0,ro,r") > + (match_operand: 2 "x86_64_hilo_general_operand" "r,o,r= ,r"))) > (clobber (reg:CC FLAGS_REG))] If we relax the requirement for TImode register pair, then =3D&r output should be used here (and in other TImode instructions) for apx_ndd ISA. Uros.