* [PATCH, i386]: Improve ffs for TARGET_BMI and macroize a couple of bitmanip patterns
@ 2016-12-15 22:48 Uros Bizjak
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From: Uros Bizjak @ 2016-12-15 22:48 UTC (permalink / raw)
To: gcc-patches
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Hello!
Attached patch improves ffs expandsion for TARGET_BMI targets.
Compared to bsf, tzcnt is noticeably faster on AMD processors.
However, since generic target enables TARGET_AVOID_FALSE_DEP_FOR_BMI,
we always expand ffs with bsf, even when using -mbmi.
Attached patch enables TARGET_AVOID_FALSE_DEP_FOR_BMI fixup also for
ffs expander, so tzcnt with eventual false-dep fixup is generated for
generic -mbmi targets.
The patch also macroizes a couple of patterns in this area.
2016-12-15 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (ffs<mode>2): Generate CCCmode flags register
for TARGET_BMI.
(ffssi2_no_cmove): Ditto.
(*tzcnt<mode>_1_falsedep_1): New insn_and_split pattern.
(*tzcnt<mode>_1_falsedep): New insn pattern.
(LT_ZCNT): New mode iterator.
(lt_zcnt): New mode attribute.
(lt_zcnt_type): New mode attribute.
(<lt_zcnt>_<mode>): Macroize expander from bmi_tzcnt_<mode> and
lzcnt_<mode> using LT_ZCNT mode iterator.
(*<lt_zcnt>_<mode>_falsedep_1): Macroize insn from
*bmi_tzcnt_<mode>_falsedep_1 and *lzcnt_<mode>_falsedep_1
using LT_ZCNT mode iterator.
(*<lt_zcnt>_<mode>_falsedep): Macroize insn from
*bmi_tzcnt_<mode>_falsedep and *lzcnt_<mode>_falsedep
using LT_ZCNT mode iterator.
(*<lt_zcnt>_<mode>): Macroize insn from *bmi_tzcnt_<mode>
and *lzcnt_<mode> using LT_ZCNT mode iterator.
* config/i386/i386-builtin.def (__builtin_ia32_tzcnt_u16)
(__builtin_ia32_tzcnt_u32, __builtin_ia32_tzcnt_u64, __builtin_ctzs):
Update for rename.
Patch was bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Committed to mainline SVN.
Uros.
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Index: config/i386/i386-builtin.def
===================================================================
--- config/i386/i386-builtin.def (revision 243716)
+++ config/i386/i386-builtin.def (working copy)
@@ -1197,11 +1197,11 @@ BDESC (OPTION_MASK_ISA_LZCNT | OPTION_MASK_ISA_64B
BDESC (OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT)
BDESC (OPTION_MASK_ISA_BMI | OPTION_MASK_ISA_64BIT, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64)
-BDESC (OPTION_MASK_ISA_BMI, CODE_FOR_bmi_tzcnt_hi, "__builtin_ia32_tzcnt_u16", IX86_BUILTIN_TZCNT16, UNKNOWN, (int) UINT16_FTYPE_UINT16)
+BDESC (OPTION_MASK_ISA_BMI, CODE_FOR_tzcnt_hi, "__builtin_ia32_tzcnt_u16", IX86_BUILTIN_TZCNT16, UNKNOWN, (int) UINT16_FTYPE_UINT16)
/* Same as above, for backward compatibility. */
-BDESC (OPTION_MASK_ISA_BMI, CODE_FOR_bmi_tzcnt_hi, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16)
-BDESC (OPTION_MASK_ISA_BMI, CODE_FOR_bmi_tzcnt_si, "__builtin_ia32_tzcnt_u32", IX86_BUILTIN_TZCNT32, UNKNOWN, (int) UINT_FTYPE_UINT)
-BDESC (OPTION_MASK_ISA_BMI | OPTION_MASK_ISA_64BIT, CODE_FOR_bmi_tzcnt_di, "__builtin_ia32_tzcnt_u64", IX86_BUILTIN_TZCNT64, UNKNOWN, (int) UINT64_FTYPE_UINT64)
+BDESC (OPTION_MASK_ISA_BMI, CODE_FOR_tzcnt_hi, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16)
+BDESC (OPTION_MASK_ISA_BMI, CODE_FOR_tzcnt_si, "__builtin_ia32_tzcnt_u32", IX86_BUILTIN_TZCNT32, UNKNOWN, (int) UINT_FTYPE_UINT)
+BDESC (OPTION_MASK_ISA_BMI | OPTION_MASK_ISA_64BIT, CODE_FOR_tzcnt_di, "__builtin_ia32_tzcnt_u64", IX86_BUILTIN_TZCNT64, UNKNOWN, (int) UINT64_FTYPE_UINT64)
/* TBM */
BDESC (OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT)
Index: config/i386/i386.md
===================================================================
--- config/i386/i386.md (revision 243716)
+++ config/i386/i386.md (working copy)
@@ -12534,8 +12534,7 @@
DONE;
}
- flags_mode
- = (TARGET_BMI && !TARGET_AVOID_FALSE_DEP_FOR_BMI) ? CCCmode : CCZmode;
+ flags_mode = TARGET_BMI ? CCCmode : CCZmode;
operands[2] = gen_reg_rtx (<MODE>mode);
operands[3] = gen_rtx_REG (flags_mode, FLAGS_REG);
@@ -12561,8 +12560,7 @@
(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
(clobber (reg:CC FLAGS_REG))])]
{
- machine_mode flags_mode
- = (TARGET_BMI && !TARGET_AVOID_FALSE_DEP_FOR_BMI) ? CCCmode : CCZmode;
+ machine_mode flags_mode = TARGET_BMI ? CCCmode : CCZmode;
operands[3] = gen_lowpart (QImode, operands[2]);
operands[4] = gen_rtx_REG (flags_mode, FLAGS_REG);
@@ -12571,6 +12569,46 @@
ix86_expand_clear (operands[2]);
})
+; False dependency happens when destination is only updated by tzcnt,
+; lzcnt or popcnt. There is no false dependency when destination is
+; also used in source.
+(define_insn_and_split "*tzcnt<mode>_1_falsedep_1"
+ [(set (reg:CCC FLAGS_REG)
+ (compare:CCC (match_operand:SWI48 1 "nonimmediate_operand" "rm")
+ (const_int 0)))
+ (set (match_operand:SWI48 0 "register_operand" "=r")
+ (ctz:SWI48 (match_dup 1)))]
+ "TARGET_BMI
+ && TARGET_AVOID_FALSE_DEP_FOR_BMI && optimize_function_for_speed_p (cfun)"
+ "#"
+ "&& reload_completed"
+ [(parallel
+ [(set (reg:CCC FLAGS_REG)
+ (compare:CCC (match_dup 1) (const_int 0)))
+ (set (match_dup 0)
+ (ctz:SWI48 (match_dup 1)))
+ (unspec [(match_dup 0)] UNSPEC_INSN_FALSE_DEP)])]
+{
+ if (!reg_mentioned_p (operands[0], operands[1]))
+ ix86_expand_clear (operands[0]);
+})
+
+(define_insn "*tzcnt<mode>_1_falsedep"
+ [(set (reg:CCC FLAGS_REG)
+ (compare:CCC (match_operand:SWI48 1 "nonimmediate_operand" "rm")
+ (const_int 0)))
+ (set (match_operand:SWI48 0 "register_operand" "=r")
+ (ctz:SWI48 (match_dup 1)))
+ (unspec [(match_operand:SWI48 2 "register_operand" "0")]
+ UNSPEC_INSN_FALSE_DEP)]
+ "TARGET_BMI"
+ "tzcnt{<imodesuffix>}\t{%1, %0|%0, %1}";
+ [(set_attr "type" "alu1")
+ (set_attr "prefix_0f" "1")
+ (set_attr "prefix_rep" "1")
+ (set_attr "btver2_decode" "double")
+ (set_attr "mode" "<MODE>")])
+
(define_insn "*tzcnt<mode>_1"
[(set (reg:CCC FLAGS_REG)
(compare:CCC (match_operand:SWI48 1 "nonimmediate_operand" "rm")
@@ -12577,7 +12615,7 @@
(const_int 0)))
(set (match_operand:SWI48 0 "register_operand" "=r")
(ctz:SWI48 (match_dup 1)))]
- "TARGET_BMI && !TARGET_AVOID_FALSE_DEP_FOR_BMI"
+ "TARGET_BMI"
"tzcnt{<imodesuffix>}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")
@@ -12619,7 +12657,7 @@
{
rtx tmp = gen_reg_rtx (HImode);
- emit_insn (gen_bmi_tzcnt_hi (tmp, operands[1]));
+ emit_insn (gen_tzcnt_hi (tmp, operands[1]));
emit_insn (gen_zero_extendhisi2 (operands[0], tmp));
DONE;
})
@@ -12695,68 +12733,41 @@
(const_string "0")))
(set_attr "mode" "<MODE>")])
-;; Version of tzcnt that is expanded from intrinsics. This version provides
-;; operand size as output when source operand is zero.
-
-(define_expand "bmi_tzcnt_<mode>"
- [(parallel
- [(set (match_operand:SWI248 0 "register_operand")
- (unspec:SWI248
- [(match_operand:SWI248 1 "nonimmediate_operand")]
- UNSPEC_TZCNT))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_BMI")
-
-; False dependency happens when destination is only updated by tzcnt,
-; lzcnt or popcnt. There is no false dependency when destination is
-; also used in source.
-(define_insn_and_split "*bmi_tzcnt_<mode>_falsedep_1"
- [(set (match_operand:SWI48 0 "register_operand" "=r")
- (unspec:SWI48
- [(match_operand:SWI48 1 "nonimmediate_operand" "rm")]
- UNSPEC_TZCNT))
+(define_insn "bsr_rex64"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (minus:DI (const_int 63)
+ (clz:DI (match_operand:DI 1 "nonimmediate_operand" "rm"))))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_BMI
- && TARGET_AVOID_FALSE_DEP_FOR_BMI && optimize_function_for_speed_p (cfun)"
- "#"
- "&& reload_completed"
- [(parallel
- [(set (match_dup 0)
- (unspec:SWI48 [(match_dup 1)] UNSPEC_TZCNT))
- (unspec [(match_dup 0)] UNSPEC_INSN_FALSE_DEP)
- (clobber (reg:CC FLAGS_REG))])]
-{
- if (!reg_mentioned_p (operands[0], operands[1]))
- ix86_expand_clear (operands[0]);
-})
+ "TARGET_64BIT"
+ "bsr{q}\t{%1, %0|%0, %1}"
+ [(set_attr "type" "alu1")
+ (set_attr "prefix_0f" "1")
+ (set_attr "znver1_decode" "vector")
+ (set_attr "mode" "DI")])
-(define_insn "*bmi_tzcnt_<mode>_falsedep"
- [(set (match_operand:SWI48 0 "register_operand" "=r")
- (unspec:SWI48
- [(match_operand:SWI48 1 "nonimmediate_operand" "rm")]
- UNSPEC_TZCNT))
- (unspec [(match_operand:SWI48 2 "register_operand" "0")]
- UNSPEC_INSN_FALSE_DEP)
+(define_insn "bsr"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (minus:SI (const_int 31)
+ (clz:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_BMI"
- "tzcnt{<imodesuffix>}\t{%1, %0|%0, %1}"
+ ""
+ "bsr{l}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")
- (set_attr "prefix_rep" "1")
- (set_attr "mode" "<MODE>")])
+ (set_attr "znver1_decode" "vector")
+ (set_attr "mode" "SI")])
-(define_insn "*bmi_tzcnt_<mode>"
- [(set (match_operand:SWI248 0 "register_operand" "=r")
- (unspec:SWI248
- [(match_operand:SWI248 1 "nonimmediate_operand" "rm")]
- UNSPEC_TZCNT))
+(define_insn "*bsrhi"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (minus:HI (const_int 15)
+ (clz:HI (match_operand:HI 1 "nonimmediate_operand" "rm"))))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_BMI"
- "tzcnt{<imodesuffix>}\t{%1, %0|%0, %1}"
+ ""
+ "bsr{w}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")
- (set_attr "prefix_rep" "1")
- (set_attr "mode" "<MODE>")])
+ (set_attr "znver1_decode" "vector")
+ (set_attr "mode" "HI")])
(define_expand "clz<mode>2"
[(parallel
@@ -12778,14 +12789,6 @@
operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)-1);
})
-(define_expand "clz<mode>2_lzcnt"
- [(parallel
- [(set (match_operand:SWI48 0 "register_operand")
- (clz:SWI48
- (match_operand:SWI48 1 "nonimmediate_operand")))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_LZCNT")
-
(define_insn_and_split "*clzhi2"
[(set (match_operand:SI 0 "register_operand")
(clz:SI
@@ -12839,9 +12842,10 @@
(set_attr "type" "bitmanip")
(set_attr "mode" "<MODE>")])
-(define_insn "*clz<mode>2_lzcnt"
+(define_insn "clz<mode>2_lzcnt"
[(set (match_operand:SWI48 0 "register_operand" "=r")
- (clz:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm")))
+ (clz:SWI48
+ (match_operand:SWI48 1 "nonimmediate_operand" "rm")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_LZCNT"
"lzcnt{<imodesuffix>}\t{%1, %0|%0, %1}"
@@ -12849,34 +12853,42 @@
(set_attr "type" "bitmanip")
(set_attr "mode" "<MODE>")])
-;; Version of lzcnt that is expanded from intrinsics. This version provides
-;; operand size as output when source operand is zero.
+(define_int_iterator LT_ZCNT
+ [(UNSPEC_TZCNT "TARGET_BMI")
+ (UNSPEC_LZCNT "TARGET_LZCNT")])
-(define_expand "lzcnt_<mode>"
+(define_int_attr lt_zcnt
+ [(UNSPEC_TZCNT "tzcnt")
+ (UNSPEC_LZCNT "lzcnt")])
+
+(define_int_attr lt_zcnt_type
+ [(UNSPEC_TZCNT "alu1")
+ (UNSPEC_LZCNT "bitmanip")])
+
+;; Version of lzcnt/tzcnt that is expanded from intrinsics. This version
+;; provides operand size as output when source operand is zero.
+
+(define_expand "<lt_zcnt>_<mode>"
[(parallel
[(set (match_operand:SWI248 0 "register_operand")
(unspec:SWI248
- [(match_operand:SWI248 1 "nonimmediate_operand")]
- UNSPEC_LZCNT))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_LZCNT")
+ [(match_operand:SWI248 1 "nonimmediate_operand")] LT_ZCNT))
+ (clobber (reg:CC FLAGS_REG))])])
; False dependency happens when destination is only updated by tzcnt,
; lzcnt or popcnt. There is no false dependency when destination is
; also used in source.
-(define_insn_and_split "*lzcnt_<mode>_falsedep_1"
+(define_insn_and_split "*<lt_zcnt>_<mode>_falsedep_1"
[(set (match_operand:SWI48 0 "register_operand" "=r")
(unspec:SWI48
- [(match_operand:SWI48 1 "nonimmediate_operand" "rm")]
- UNSPEC_LZCNT))
+ [(match_operand:SWI48 1 "nonimmediate_operand" "rm")] LT_ZCNT))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_LZCNT
- && TARGET_AVOID_FALSE_DEP_FOR_BMI && optimize_function_for_speed_p (cfun)"
+ "TARGET_AVOID_FALSE_DEP_FOR_BMI && optimize_function_for_speed_p (cfun)"
"#"
"&& reload_completed"
[(parallel
[(set (match_dup 0)
- (unspec:SWI48 [(match_dup 1)] UNSPEC_LZCNT))
+ (unspec:SWI48 [(match_dup 1)] LT_ZCNT))
(unspec [(match_dup 0)] UNSPEC_INSN_FALSE_DEP)
(clobber (reg:CC FLAGS_REG))])]
{
@@ -12884,30 +12896,28 @@
ix86_expand_clear (operands[0]);
})
-(define_insn "*lzcnt_<mode>_falsedep"
+(define_insn "*<lt_zcnt>_<mode>_falsedep"
[(set (match_operand:SWI48 0 "register_operand" "=r")
(unspec:SWI48
- [(match_operand:SWI48 1 "nonimmediate_operand" "rm")]
- UNSPEC_LZCNT))
+ [(match_operand:SWI48 1 "nonimmediate_operand" "rm")] LT_ZCNT))
(unspec [(match_operand:SWI48 2 "register_operand" "0")]
UNSPEC_INSN_FALSE_DEP)
(clobber (reg:CC FLAGS_REG))]
- "TARGET_LZCNT"
- "lzcnt{<imodesuffix>}\t{%1, %0|%0, %1}"
- [(set_attr "type" "alu1")
+ ""
+ "<lt_zcnt>{<imodesuffix>}\t{%1, %0|%0, %1}"
+ [(set_attr "type" "<lt_zcnt_type>")
(set_attr "prefix_0f" "1")
(set_attr "prefix_rep" "1")
(set_attr "mode" "<MODE>")])
-(define_insn "*lzcnt_<mode>"
+(define_insn "*<lt_zcnt>_<mode>"
[(set (match_operand:SWI248 0 "register_operand" "=r")
(unspec:SWI248
- [(match_operand:SWI248 1 "nonimmediate_operand" "rm")]
- UNSPEC_LZCNT))
+ [(match_operand:SWI248 1 "nonimmediate_operand" "rm")] LT_ZCNT))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_LZCNT"
- "lzcnt{<imodesuffix>}\t{%1, %0|%0, %1}"
- [(set_attr "type" "alu1")
+ ""
+ "<lt_zcnt>{<imodesuffix>}\t{%1, %0|%0, %1}"
+ [(set_attr "type" "<lt_zcnt_type>")
(set_attr "prefix_0f" "1")
(set_attr "prefix_rep" "1")
(set_attr "mode" "<MODE>")])
@@ -13206,42 +13216,6 @@
[(set_attr "type" "bitmanip")
(set_attr "mode" "<MODE>")])
-(define_insn "bsr_rex64"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (minus:DI (const_int 63)
- (clz:DI (match_operand:DI 1 "nonimmediate_operand" "rm"))))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT"
- "bsr{q}\t{%1, %0|%0, %1}"
- [(set_attr "type" "alu1")
- (set_attr "prefix_0f" "1")
- (set_attr "znver1_decode" "vector")
- (set_attr "mode" "DI")])
-
-(define_insn "bsr"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (minus:SI (const_int 31)
- (clz:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))))
- (clobber (reg:CC FLAGS_REG))]
- ""
- "bsr{l}\t{%1, %0|%0, %1}"
- [(set_attr "type" "alu1")
- (set_attr "prefix_0f" "1")
- (set_attr "znver1_decode" "vector")
- (set_attr "mode" "SI")])
-
-(define_insn "*bsrhi"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (minus:HI (const_int 15)
- (clz:HI (match_operand:HI 1 "nonimmediate_operand" "rm"))))
- (clobber (reg:CC FLAGS_REG))]
- ""
- "bsr{w}\t{%1, %0|%0, %1}"
- [(set_attr "type" "alu1")
- (set_attr "prefix_0f" "1")
- (set_attr "znver1_decode" "vector")
- (set_attr "mode" "HI")])
-
(define_expand "popcount<mode>2"
[(parallel
[(set (match_operand:SWI248 0 "register_operand")
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2016-12-15 22:48 [PATCH, i386]: Improve ffs for TARGET_BMI and macroize a couple of bitmanip patterns Uros Bizjak
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