From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 53708 invoked by alias); 26 May 2016 17:39:14 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 52841 invoked by uid 89); 26 May 2016 17:39:13 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 spammy=pleasant, counting X-HELO: mail-vk0-f45.google.com Received: from mail-vk0-f45.google.com (HELO mail-vk0-f45.google.com) (209.85.213.45) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Thu, 26 May 2016 17:39:03 +0000 Received: by mail-vk0-f45.google.com with SMTP id c189so111819073vkb.1 for ; Thu, 26 May 2016 10:39:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc; bh=OTVhrOfHvPU6lS3zOkjVtAHrC93DxY5KH3VjdNRoLQw=; b=JaANJRs+rmYo3LQ3b0po+LnLowLfOLdhLwmpHz6Z/ywN3IOa0t3fBEiiBHBhIjEwBn ihXEhF1TCOCjTQyEq0WzlvjsUdNII3PuNrm/CKYd+/navRWdQ235muTPgkunLV5Itk/C cbl1xF41mqIAQ7HEqBWSJnBwLoj28oPFpqqw8eaSHGTFld7XKnKz3G4H+PuexL1y5H/n pM+qfClkK5xAi/9/lXwC7UZRK65LwjdnK0Xqrc5SqgP7jXBu/mJkogTa8bIaq6NNyHL4 t6Hw1U/XGQaCsJ43T9eM0sxTPafNgmIp845nwgXcgTmrOpwaWNHACQWEaAHRWLoQu8vk rh4A== X-Gm-Message-State: ALyK8tIDQvcGFpLwGv0oiqHn79fqviaIDOFRZ0eNkRUgTHCJhCtcoTpGgJjt+FplU0PHvyFO3pKDc9ISQ3iJ9Q== MIME-Version: 1.0 X-Received: by 10.176.2.139 with SMTP id 11mr6207010uah.6.1464284341084; Thu, 26 May 2016 10:39:01 -0700 (PDT) Received: by 10.103.72.206 with HTTP; Thu, 26 May 2016 10:39:01 -0700 (PDT) In-Reply-To: <20160526170545.GZ28550@tucnak.redhat.com> References: <20160526170545.GZ28550@tucnak.redhat.com> Date: Fri, 27 May 2016 02:14:00 -0000 Message-ID: Subject: Re: [PATCH] Improve *vec_concatv2si_sse4_1 From: Uros Bizjak To: Jakub Jelinek Cc: Kirill Yukhin , "gcc-patches@gcc.gnu.org" Content-Type: text/plain; charset=UTF-8 X-SW-Source: 2016-05/txt/msg02135.txt.bz2 On Thu, May 26, 2016 at 7:05 PM, Jakub Jelinek wrote: > Hi! > > This patch adds an avx512dq alternative (EVEX vpinsrd requires that) and > enables EVEX vmovd and vpunpckldq. > > Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? > > 2016-05-26 Jakub Jelinek > > * config/i386/sse.md (*vec_concatv2si_sse4_1): Add avx512dq v=Yv,rm > alternative. Change x=x,x alternative to v=Yv,Yv and x=rm,C > alternative to v=rm,C. > > * gcc.target/i386/avx512dq-concatv2si-1.c: New test. > * gcc.target/i386/avx512vl-concatv2si-1.c: New test. Ouch, I have just changed these mega strings in attribute definitions to something more readable. Can you please redo the attribute part? It should be much more pleasant experience than counting all the commas...). Uros. > --- gcc/config/i386/sse.md.jj 2016-05-26 10:44:25.000000000 +0200 > +++ gcc/config/i386/sse.md 2016-05-26 14:22:26.819313220 +0200 > @@ -13339,29 +13339,30 @@ (define_split > > (define_insn "*vec_concatv2si_sse4_1" > [(set (match_operand:V2SI 0 "register_operand" > - "=Yr,*x,x, Yr,*x,x, x, *y,*y") > + "=Yr,*x, x, v,Yr,*x, v, v, *y,*y") > (vec_concat:V2SI > (match_operand:SI 1 "nonimmediate_operand" > - " 0, 0,x, 0,0, x,rm, 0,rm") > + " 0, 0, x,Yv, 0, 0,Yv,rm, 0,rm") > (match_operand:SI 2 "vector_move_operand" > - " rm,rm,rm,Yr,*x,x, C,*ym, C")))] > + " rm,rm,rm,rm,Yr,*x,Yv, C,*ym, C")))] > "TARGET_SSE4_1 && !(MEM_P (operands[1]) && MEM_P (operands[2]))" > "@ > pinsrd\t{$1, %2, %0|%0, %2, 1} > pinsrd\t{$1, %2, %0|%0, %2, 1} > vpinsrd\t{$1, %2, %1, %0|%0, %1, %2, 1} > + vpinsrd\t{$1, %2, %1, %0|%0, %1, %2, 1} > punpckldq\t{%2, %0|%0, %2} > punpckldq\t{%2, %0|%0, %2} > vpunpckldq\t{%2, %1, %0|%0, %1, %2} > %vmovd\t{%1, %0|%0, %1} > punpckldq\t{%2, %0|%0, %2} > movd\t{%1, %0|%0, %1}" > - [(set_attr "isa" "noavx,noavx,avx,noavx,noavx,avx,*,*,*") > - (set_attr "type" "sselog,sselog,sselog,sselog,sselog,sselog,ssemov,mmxcvt,mmxmov") > - (set_attr "prefix_extra" "1,1,1,*,*,*,*,*,*") > - (set_attr "length_immediate" "1,1,1,*,*,*,*,*,*") > - (set_attr "prefix" "orig,orig,vex,orig,orig,vex,maybe_vex,orig,orig") > - (set_attr "mode" "TI,TI,TI,TI,TI,TI,TI,DI,DI")]) > + [(set_attr "isa" "noavx,noavx,avx,avx512dq,noavx,noavx,avx,*,*,*") > + (set_attr "type" "sselog,sselog,sselog,sselog,sselog,sselog,sselog,ssemov,mmxcvt,mmxmov") > + (set_attr "prefix_extra" "1,1,1,1,*,*,*,*,*,*") > + (set_attr "length_immediate" "1,1,1,1,*,*,*,*,*,*") > + (set_attr "prefix" "orig,orig,vex,evex,orig,orig,maybe_evex,maybe_vex,orig,orig") > + (set_attr "mode" "TI,TI,TI,TI,TI,TI,TI,TI,DI,DI")]) > > ;; ??? In theory we can match memory for the MMX alternative, but allowing > ;; nonimmediate_operand for operand 2 and *not* allowing memory for the SSE > --- gcc/testsuite/gcc.target/i386/avx512dq-concatv2si-1.c.jj 2016-05-26 15:14:55.853786550 +0200 > +++ gcc/testsuite/gcc.target/i386/avx512dq-concatv2si-1.c 2016-05-26 15:13:57.000000000 +0200 > @@ -0,0 +1,43 @@ > +/* { dg-do compile { target { ! ia32 } } } */ > +/* { dg-options "-O2 -mavx512vl -mavx512dq -masm=att" } */ > + > +typedef int V __attribute__((vector_size (8))); > + > +void > +f1 (int x, int y) > +{ > + register int a __asm ("xmm16"); > + register int b __asm ("xmm17"); > + register V c __asm ("xmm3"); > + a = x; > + b = y; > + asm volatile ("" : "+v" (a), "+v" (b)); > + c = (V) { a, b }; > + asm volatile ("" : "+v" (c)); > +} > + > +/* { dg-final { scan-assembler "vpunpckldq\[^\n\r]*%xmm17\[^\n\r]*%xmm16\[^\n\r]*%xmm3" } } */ > + > +void > +f2 (int x, int y) > +{ > + register int a __asm ("xmm16"); > + register V c __asm ("xmm3"); > + a = x; > + asm volatile ("" : "+v" (a)); > + c = (V) { a, y }; > + asm volatile ("" : "+v" (c)); > +} > + > +void > +f3 (int x, int *y) > +{ > + register int a __asm ("xmm16"); > + register V c __asm ("xmm3"); > + a = x; > + asm volatile ("" : "+v" (a)); > + c = (V) { a, *y }; > + asm volatile ("" : "+v" (c)); > +} > + > +/* { dg-final { scan-assembler-times "vpinsrd\[^\n\r]*\\\$1\[^\n\r]*%xmm16\[^\n\r]*%xmm3" 2 } } */ > --- gcc/testsuite/gcc.target/i386/avx512vl-concatv2si-1.c.jj 2016-05-26 15:15:11.921574803 +0200 > +++ gcc/testsuite/gcc.target/i386/avx512vl-concatv2si-1.c 2016-05-26 15:16:24.936612585 +0200 > @@ -0,0 +1,43 @@ > +/* { dg-do compile { target { ! ia32 } } } */ > +/* { dg-options "-O2 -mavx512vl -mno-avx512dq -masm=att" } */ > + > +typedef int V __attribute__((vector_size (8))); > + > +void > +f1 (int x, int y) > +{ > + register int a __asm ("xmm16"); > + register int b __asm ("xmm17"); > + register V c __asm ("xmm3"); > + a = x; > + b = y; > + asm volatile ("" : "+v" (a), "+v" (b)); > + c = (V) { a, b }; > + asm volatile ("" : "+v" (c)); > +} > + > +/* { dg-final { scan-assembler "vpunpckldq\[^\n\r]*%xmm17\[^\n\r]*%xmm16\[^\n\r]*%xmm3" } } */ > + > +void > +f2 (int x, int y) > +{ > + register int a __asm ("xmm16"); > + register V c __asm ("xmm3"); > + a = x; > + asm volatile ("" : "+v" (a)); > + c = (V) { a, y }; > + asm volatile ("" : "+v" (c)); > +} > + > +void > +f3 (int x, int *y) > +{ > + register int a __asm ("xmm16"); > + register V c __asm ("xmm3"); > + a = x; > + asm volatile ("" : "+v" (a)); > + c = (V) { a, *y }; > + asm volatile ("" : "+v" (c)); > +} > + > +/* { dg-final { scan-assembler-not "vpinsrd\[^\n\r]*\\\$1\[^\n\r]*%xmm16\[^\n\r]*%xmm3" } } */ > > Jakub