From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qv1-xf36.google.com (mail-qv1-xf36.google.com [IPv6:2607:f8b0:4864:20::f36]) by sourceware.org (Postfix) with ESMTPS id 111A7385842B for ; Mon, 28 Mar 2022 08:09:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 111A7385842B Received: by mail-qv1-xf36.google.com with SMTP id e22so11235709qvf.9 for ; Mon, 28 Mar 2022 01:09:30 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=oTA4mMpGrcOXY4dH2JPRC0Ca4BNT1T/VZuFdEfXqPUg=; b=c2Z98qB+dKd40WEYcpxtOE5iyv4bDVQwSFDSeC5aMzXAr85lzzDJ/+yYfrrPteYspg DJc6X8q76xfKjAk1Hunubk+N7HG+2NSic9z/wTg+zfxt7f42eKpswmEmR3eBDYaXKe7D +9GIhdN6LpP/khg4oDcQyYeRvmApzTktiH8DnVP76PJhhvTVhJdUNmaktZctdD12U0PF mQBpZ6elPYaPrmwFxovKp83TQsQho5b7fUtDY9aetAbLLguyxq1Bxsj85lQTpOHEpkJj TMVuBNizTJWoc21HbYOwMS9YL0wOWLuB2Ueg6E2KYMbds7sqF0k/74XbjLTvCAdvuvFs hXxg== X-Gm-Message-State: AOAM531XaZ7D9bRcFUUVQJDZ1v7r9wodhSgjOXRwjzB9Z4ivD2F+moQJ /nYOemPspg5kC9tG4/3l9RqGnMCFVOuFnBoSwqM= X-Google-Smtp-Source: ABdhPJwsdeKjXQXCaYnhQXaZiX84Z0nrp3kXBXc5uvfnX+HZyhWuCS9pLYJR5pWIB4Ciuycl0yd1qe+HqRYEgz04bR0= X-Received: by 2002:ad4:5dca:0:b0:441:55db:2835 with SMTP id m10-20020ad45dca000000b0044155db2835mr19678804qvh.31.1648454969349; Mon, 28 Mar 2022 01:09:29 -0700 (PDT) MIME-Version: 1.0 References: <20220328045522.52318-1-hongtao.liu@intel.com> In-Reply-To: <20220328045522.52318-1-hongtao.liu@intel.com> From: Uros Bizjak Date: Mon, 28 Mar 2022 10:09:18 +0200 Message-ID: Subject: Re: [PATCH] [i386] Fix typo in vec_setv8hi_0. To: liuhongt Cc: "gcc-patches@gcc.gnu.org" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 Mar 2022 08:09:32 -0000 On Mon, Mar 28, 2022 at 6:55 AM liuhongt wrote: > > pinsrw is available for both reg and mem operand under sse2. > pextrw requires sse4.1 for mem operands. > > The patch change attr "isa" for pinsrw mem alternative from sse4_noavx > to noavx, will enable below optimization. > > - movzwl (%rdi), %eax > pxor %xmm1, %xmm1 > - pinsrw $0, %eax, %xmm1 > + pinsrw $0, (%rdi), %xmm1 > movdqa %xmm1, %xmm0 > > Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. > Ok for trunk? > > gcc/ChangeLog: > > PR target/105066 > * config/i386/sse.md (vec_set_0): Change attr "isa" of > alternative 4 from sse4_noavx to noavx. > > gcc/testsuite/ChangeLog: > > * gcc.target/i386/pr105066.c: New test. OK. Thanks, Uros. > --- > gcc/config/i386/sse.md | 4 ++-- > gcc/testsuite/gcc.target/i386/pr105066.c | 10 ++++++++++ > 2 files changed, 12 insertions(+), 2 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/i386/pr105066.c > > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md > index a9e18d38323..27e9629f4b0 100644 > --- a/gcc/config/i386/sse.md > +++ b/gcc/config/i386/sse.md > @@ -10617,9 +10617,9 @@ (define_insn "vec_set_0" > [(set (attr "isa") > (cond [(eq_attr "alternative" "0,1,2") > (const_string "avx512fp16") > - (eq_attr "alternative" "3") > + (eq_attr "alternative" "3,4") > (const_string "noavx") > - (eq_attr "alternative" "4,5,6") > + (eq_attr "alternative" "5,6") > (const_string "sse4_noavx") > (eq_attr "alternative" "7,8,9") > (const_string "avx") > diff --git a/gcc/testsuite/gcc.target/i386/pr105066.c b/gcc/testsuite/gcc.target/i386/pr105066.c > new file mode 100644 > index 00000000000..c5c5b9e12de > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/pr105066.c > @@ -0,0 +1,10 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -msse2 -mno-sse4.1" } */ > +/* { dg-final { scan-assembler-not "movzwl" } } */ > +/* { dg-final { scan-assembler {(?n)pinsrw[ \t]+\$0.*\(%} } } */ > + > +#include > + > +__m128i load16(void *p){ > + return _mm_loadu_si16(p); > +} > -- > 2.18.1 >