From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 25114 invoked by alias); 12 Feb 2019 13:43:09 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 25102 invoked by uid 89); 12 Feb 2019 13:43:08 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00,FREEMAIL_FROM,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-it1-f180.google.com Received: from mail-it1-f180.google.com (HELO mail-it1-f180.google.com) (209.85.166.180) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 12 Feb 2019 13:43:06 +0000 Received: by mail-it1-f180.google.com with SMTP id r11so7241364itc.2 for ; Tue, 12 Feb 2019 05:43:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=TThpZm3viERK/6aqP4NYD4ozoVXIqlmUmnOxGFu2ivo=; b=n/4KGb1Mf+lZfc6D9dt1LKTaHxOmyluYNFwObSldXIGKRXwy+tfDHE+sx3hmJ38DXn b7iGiPurbtCgh75QmoarTCcORcvabqCd4N7b7Wmm2Y/dLDhsTieJ+8WxRXjRJZtEPBOH 71i2NIhh1V3V/DUtGdTv/I6/s3HM1qVVTcz/LhZVC6tpubB02kaeZoOMU9SvYw6ol1JS I55DetgsGSMC829of5y2Bz0TOgzdnCCyvZW2vVVu4552n/cuwgxzUQ4REGWmeV6wHPH+ xtTK+FMQHCmaJ02dOWGvk8is81lD4X5WSSHP2twX5EQPXcuZzIqei58iBk0JTl7vRDC8 rMXQ== MIME-Version: 1.0 References: <20190211225553.32050-1-hjl.tools@gmail.com> <20190211225553.32050-37-hjl.tools@gmail.com> In-Reply-To: <20190211225553.32050-37-hjl.tools@gmail.com> From: Uros Bizjak Date: Tue, 12 Feb 2019 13:43:00 -0000 Message-ID: Subject: Re: [PATCH 36/40] i386: Allow MMX vector expanders with TARGET_MMX_WITH_SSE To: "H.J. Lu" Cc: "gcc-patches@gcc.gnu.org" Content-Type: text/plain; charset="UTF-8" X-SW-Source: 2019-02/txt/msg00886.txt.bz2 On Mon, Feb 11, 2019 at 11:55 PM H.J. Lu wrote: > > PR target/89021 > * config/i386/i386.c (ix86_expand_vector_init_duplicate): Set > mmx_ok to true if TARGET_MMX_WITH_SSE is true. > (ix86_expand_vector_init_one_nonzero): Likewise. > (ix86_expand_vector_init_one_var): Likewise. > (ix86_expand_vector_init_general): Likewise. > (ix86_expand_vector_init): Likewise. > (ix86_expand_vector_set): Likewise. > (ix86_expand_vector_extract): Likewise. > * config/i386/mmx.md (*vec_dupv2sf): Changed to > define_insn_and_split to support SSE emulation. > (vec_setv2sf): Also allow TARGET_MMX_WITH_SSE. > (vec_extractv2sf_1 splitter): Likewise. > (vec_extractv2sfsf): Likewise. > (vec_setv2si): Likewise. > (vec_extractv2si_1 splitter): Likewise. > (vec_extractv2sisi): Likewise. > (vec_setv4hi): Likewise. > (vec_extractv4hihi): Likewise. > (vec_setv8qi): Likewise. > (vec_extractv8qiqi): Likewise. > (*vec_extractv2sf_0): Don't allow TARGET_MMX_WITH_SSE. > (*vec_extractv2sf_1): Likewise. > (*vec_extractv2si_0): Likewise. > (*vec_extractv2si_1): Likewise. > (*vec_extractv2sf_0_sse): New. > (*vec_extractv2sf_1_sse): Likewise. > (*vec_extractv2si_0_sse): Likewise. > (*vec_extractv2si_1_sse): Likewise. Please do not introduce new *_sse patterns, use mmx_isa attribute to disable unwanted alternatives. > --- > gcc/config/i386/i386.c | 8 +++ > gcc/config/i386/mmx.md | 129 +++++++++++++++++++++++++++++++++-------- > 2 files changed, 113 insertions(+), 24 deletions(-) > > diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c > index 7d65192c1cd..4e776b8c3ea 100644 > --- a/gcc/config/i386/i386.c > +++ b/gcc/config/i386/i386.c > @@ -42365,6 +42365,7 @@ ix86_expand_vector_init_duplicate (bool mmx_ok, machine_mode mode, > { > bool ok; > > + mmx_ok |= TARGET_MMX_WITH_SSE; > switch (mode) > { > case E_V2SImode: > @@ -42524,6 +42525,7 @@ ix86_expand_vector_init_one_nonzero (bool mmx_ok, machine_mode mode, > bool use_vector_set = false; > rtx (*gen_vec_set_0) (rtx, rtx, rtx) = NULL; > > + mmx_ok |= TARGET_MMX_WITH_SSE; > switch (mode) > { > case E_V2DImode: > @@ -42717,6 +42719,7 @@ ix86_expand_vector_init_one_var (bool mmx_ok, machine_mode mode, > XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode)); > const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0)); > > + mmx_ok |= TARGET_MMX_WITH_SSE; > switch (mode) > { > case E_V2DFmode: > @@ -43102,6 +43105,7 @@ ix86_expand_vector_init_general (bool mmx_ok, machine_mode mode, > machine_mode quarter_mode = VOIDmode; > int n, i; > > + mmx_ok |= TARGET_MMX_WITH_SSE; > switch (mode) > { > case E_V2SFmode: > @@ -43301,6 +43305,8 @@ ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals) > int i; > rtx x; > > + mmx_ok |= TARGET_MMX_WITH_SSE; > + > /* Handle first initialization from vector elts. */ > if (n_elts != XVECLEN (vals, 0)) > { > @@ -43400,6 +43406,7 @@ ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt) > machine_mode mmode = VOIDmode; > rtx (*gen_blendm) (rtx, rtx, rtx, rtx); > > + mmx_ok |= TARGET_MMX_WITH_SSE; > switch (mode) > { > case E_V2SFmode: > @@ -43755,6 +43762,7 @@ ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt) > bool use_vec_extr = false; > rtx tmp; > > + mmx_ok |= TARGET_MMX_WITH_SSE; > switch (mode) > { > case E_V2SImode: > diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md > index c8bd544dc9e..4e8b6e54b4c 100644 > --- a/gcc/config/i386/mmx.md > +++ b/gcc/config/i386/mmx.md > @@ -591,14 +591,23 @@ > (set_attr "prefix_extra" "1") > (set_attr "mode" "V2SF")]) > > -(define_insn "*vec_dupv2sf" > - [(set (match_operand:V2SF 0 "register_operand" "=y") > +(define_insn_and_split "*vec_dupv2sf" > + [(set (match_operand:V2SF 0 "register_operand" "=y,x,Yv") > (vec_duplicate:V2SF > - (match_operand:SF 1 "register_operand" "0")))] > - "TARGET_MMX" > - "punpckldq\t%0, %0" > - [(set_attr "type" "mmxcvt") > - (set_attr "mode" "DI")]) > + (match_operand:SF 1 "register_operand" "0,0,Yv")))] > + "TARGET_MMX || TARGET_MMX_WITH_SSE" > + "@ > + punpckldq\t%0, %0 > + # > + #" > + "TARGET_MMX_WITH_SSE && reload_completed" > + [(set (match_dup 0) > + (vec_duplicate:V4SF (match_dup 1)))] > + "operands[0] = lowpart_subreg (V4SFmode, operands[0], > + GET_MODE (operands[0]));" > + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") > + (set_attr "type" "mmxcvt,ssemov,ssemov") > + (set_attr "mode" "DI,TI,TI")]) > > (define_insn "*mmx_concatv2sf" > [(set (match_operand:V2SF 0 "register_operand" "=y,y") > @@ -616,7 +625,7 @@ > [(match_operand:V2SF 0 "register_operand") > (match_operand:SF 1 "register_operand") > (match_operand 2 "const_int_operand")] > - "TARGET_MMX" > + "TARGET_MMX || TARGET_MMX_WITH_SSE" > { > ix86_expand_vector_set (false, operands[0], operands[1], > INTVAL (operands[2])); > @@ -630,7 +639,20 @@ > (vec_select:SF > (match_operand:V2SF 1 "nonimmediate_operand" " xm,x,ym,y,m,m") > (parallel [(const_int 0)])))] > - "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))" > + "TARGET_MMX > + && !TARGET_MMX_WITH_SSE > + && !(MEM_P (operands[0]) && MEM_P (operands[1]))" > + "#" > + "&& reload_completed" > + [(set (match_dup 0) (match_dup 1))] > + "operands[1] = gen_lowpart (SFmode, operands[1]);") > + > +(define_insn_and_split "*vec_extractv2sf_0_sse" > + [(set (match_operand:SF 0 "nonimmediate_operand" "=x, m,f,r") > + (vec_select:SF > + (match_operand:V2SF 1 "nonimmediate_operand" " xm,x,m,m") > + (parallel [(const_int 0)])))] > + "TARGET_MMX_WITH_SSE && !(MEM_P (operands[0]) && MEM_P (operands[1]))" > "#" > "&& reload_completed" > [(set (match_dup 0) (match_dup 1))] > @@ -643,7 +665,9 @@ > (vec_select:SF > (match_operand:V2SF 1 "nonimmediate_operand" " 0,x,x,o,o,o,o") > (parallel [(const_int 1)])))] > - "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))" > + "TARGET_MMX > + && !TARGET_MMX_WITH_SSE > + && !(MEM_P (operands[0]) && MEM_P (operands[1]))" > "@ > punpckhdq\t%0, %0 > %vmovshdup\t{%1, %0|%0, %1} > @@ -665,12 +689,33 @@ > (set_attr "prefix" "orig,maybe_vex,orig,orig,orig,orig,orig") > (set_attr "mode" "DI,V4SF,V4SF,SF,SF,SF,SF")]) > > +(define_insn "*vec_extractv2sf_1_sse" > + [(set (match_operand:SF 0 "nonimmediate_operand" "=x,x,x,f,r") > + (vec_select:SF > + (match_operand:V2SF 1 "nonimmediate_operand" " x,x,o,o,o") > + (parallel [(const_int 1)])))] > + "TARGET_MMX_WITH_SSE && !(MEM_P (operands[0]) && MEM_P (operands[1]))" > + "@ > + %vmovshdup\t{%1, %0|%0, %1} > + shufps\t{$0xe5, %1, %0|%0, %1, 0xe5} > + # > + # > + #" > + [(set_attr "isa" "sse3,noavx,*,*,*") > + (set_attr "type" "sse,sseshuf1,ssemov,fmov,imov") > + (set (attr "length_immediate") > + (if_then_else (eq_attr "alternative" "1") > + (const_string "1") > + (const_string "*"))) > + (set_attr "prefix" "maybe_vex,orig,orig,orig,orig") > + (set_attr "mode" "V4SF,V4SF,SF,SF,SF")]) > + > (define_split > [(set (match_operand:SF 0 "register_operand") > (vec_select:SF > (match_operand:V2SF 1 "memory_operand") > (parallel [(const_int 1)])))] > - "TARGET_MMX && reload_completed" > + "(TARGET_MMX || TARGET_MMX_WITH_SSE) && reload_completed" > [(set (match_dup 0) (match_dup 1))] > "operands[1] = adjust_address (operands[1], SFmode, 4);") > > @@ -678,7 +723,7 @@ > [(match_operand:SF 0 "register_operand") > (match_operand:V2SF 1 "register_operand") > (match_operand 2 "const_int_operand")] > - "TARGET_MMX" > + "TARGET_MMX || TARGET_MMX_WITH_SSE" > { > ix86_expand_vector_extract (false, operands[0], operands[1], > INTVAL (operands[2])); > @@ -1574,7 +1619,7 @@ > [(match_operand:V2SI 0 "register_operand") > (match_operand:SI 1 "register_operand") > (match_operand 2 "const_int_operand")] > - "TARGET_MMX" > + "TARGET_MMX || TARGET_MMX_WITH_SSE" > { > ix86_expand_vector_set (false, operands[0], operands[1], > INTVAL (operands[2])); > @@ -1588,7 +1633,20 @@ > (vec_select:SI > (match_operand:V2SI 1 "nonimmediate_operand" "xm,x,ym,y,m") > (parallel [(const_int 0)])))] > - "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))" > + "TARGET_MMX > + && !TARGET_MMX_WITH_SSE > + && !(MEM_P (operands[0]) && MEM_P (operands[1]))" > + "#" > + "&& reload_completed" > + [(set (match_dup 0) (match_dup 1))] > + "operands[1] = gen_lowpart (SImode, operands[1]);") > + > +(define_insn_and_split "*vec_extractv2si_0_sse" > + [(set (match_operand:SI 0 "nonimmediate_operand" "=x,m,r") > + (vec_select:SI > + (match_operand:V2SI 1 "nonimmediate_operand" "xm,x,m") > + (parallel [(const_int 0)])))] > + "TARGET_MMX_WITH_SSE && !(MEM_P (operands[0]) && MEM_P (operands[1]))" > "#" > "&& reload_completed" > [(set (match_dup 0) (match_dup 1))] > @@ -1601,7 +1659,9 @@ > (vec_select:SI > (match_operand:V2SI 1 "nonimmediate_operand" " 0,x,x,o,o,o") > (parallel [(const_int 1)])))] > - "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))" > + "TARGET_MMX > + && !TARGET_MMX_WITH_SSE > + && !(MEM_P (operands[0]) && MEM_P (operands[1]))" > "@ > punpckhdq\t%0, %0 > %vpshufd\t{$0xe5, %1, %0|%0, %1, 0xe5} > @@ -1618,22 +1678,43 @@ > (set_attr "prefix" "orig,maybe_vex,orig,orig,orig,orig") > (set_attr "mode" "DI,TI,V4SF,SI,SI,SI")]) > > +(define_insn "*vec_extractv2si_1_sse" > + [(set (match_operand:SI 0 "nonimmediate_operand" "=x,x,x,r") > + (vec_select:SI > + (match_operand:V2SI 1 "nonimmediate_operand" " x,x,o,o") > + (parallel [(const_int 1)])))] > + "TARGET_MMX_WITH_SSE > + && !(MEM_P (operands[0]) && MEM_P (operands[1]))" > + "@ > + %vpshufd\t{$0xe5, %1, %0|%0, %1, 0xe5} > + shufps\t{$0xe5, %1, %0|%0, %1, 0xe5} > + # > + #" > + [(set_attr "isa" "sse2,noavx,*,*") > + (set_attr "type" "sseshuf1,sseshuf1,ssemov,imov") > + (set (attr "length_immediate") > + (if_then_else (eq_attr "alternative" "0,1") > + (const_string "1") > + (const_string "*"))) > + (set_attr "prefix" "maybe_vex,orig,orig,orig") > + (set_attr "mode" "TI,V4SF,SI,SI")]) > + > (define_split > [(set (match_operand:SI 0 "register_operand") > (vec_select:SI > (match_operand:V2SI 1 "memory_operand") > (parallel [(const_int 1)])))] > - "TARGET_MMX && reload_completed" > + "(TARGET_MMX || TARGET_MMX_WITH_SSE) && reload_completed" > [(set (match_dup 0) (match_dup 1))] > "operands[1] = adjust_address (operands[1], SImode, 4);") > > (define_insn_and_split "*vec_extractv2si_zext_mem" > - [(set (match_operand:DI 0 "register_operand" "=y,x,r") > + [(set (match_operand:DI 0 "register_operand" "=x,r") > (zero_extend:DI > (vec_select:SI > - (match_operand:V2SI 1 "memory_operand" "o,o,o") > + (match_operand:V2SI 1 "memory_operand" "o,o") > (parallel [(match_operand:SI 2 "const_0_to_1_operand")]))))] > - "TARGET_64BIT && TARGET_MMX" > + "TARGET_64BIT" Here you need TARGET_64BIT && (TARGET_MMX || TARGET_MMX_WITH_SSE) and mmx_isa attribute. Uros. > "#" > "&& reload_completed" > [(set (match_dup 0) (zero_extend:DI (match_dup 1)))] > @@ -1645,7 +1726,7 @@ > [(match_operand:SI 0 "register_operand") > (match_operand:V2SI 1 "register_operand") > (match_operand 2 "const_int_operand")] > - "TARGET_MMX" > + "TARGET_MMX || TARGET_MMX_WITH_SSE" > { > ix86_expand_vector_extract (false, operands[0], operands[1], > INTVAL (operands[2])); > @@ -1665,7 +1746,7 @@ > [(match_operand:V4HI 0 "register_operand") > (match_operand:HI 1 "register_operand") > (match_operand 2 "const_int_operand")] > - "TARGET_MMX" > + "TARGET_MMX || TARGET_MMX_WITH_SSE" > { > ix86_expand_vector_set (false, operands[0], operands[1], > INTVAL (operands[2])); > @@ -1676,7 +1757,7 @@ > [(match_operand:HI 0 "register_operand") > (match_operand:V4HI 1 "register_operand") > (match_operand 2 "const_int_operand")] > - "TARGET_MMX" > + "TARGET_MMX || TARGET_MMX_WITH_SSE" > { > ix86_expand_vector_extract (false, operands[0], operands[1], > INTVAL (operands[2])); > @@ -1696,7 +1777,7 @@ > [(match_operand:V8QI 0 "register_operand") > (match_operand:QI 1 "register_operand") > (match_operand 2 "const_int_operand")] > - "TARGET_MMX" > + "TARGET_MMX || TARGET_MMX_WITH_SSE" > { > ix86_expand_vector_set (false, operands[0], operands[1], > INTVAL (operands[2])); > @@ -1707,7 +1788,7 @@ > [(match_operand:QI 0 "register_operand") > (match_operand:V8QI 1 "register_operand") > (match_operand 2 "const_int_operand")] > - "TARGET_MMX" > + "TARGET_MMX || TARGET_MMX_WITH_SSE" > { > ix86_expand_vector_extract (false, operands[0], operands[1], > INTVAL (operands[2])); > -- > 2.20.1 >