From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 23061 invoked by alias); 10 Oct 2014 16:37:13 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 23050 invoked by uid 89); 10 Oct 2014 16:37:13 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-lb0-f171.google.com Received: from mail-lb0-f171.google.com (HELO mail-lb0-f171.google.com) (209.85.217.171) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Fri, 10 Oct 2014 16:37:12 +0000 Received: by mail-lb0-f171.google.com with SMTP id z12so3408297lbi.2 for ; Fri, 10 Oct 2014 09:37:07 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.112.78.38 with SMTP id y6mr4552892lbw.94.1412959027766; Fri, 10 Oct 2014 09:37:07 -0700 (PDT) Received: by 10.152.8.103 with HTTP; Fri, 10 Oct 2014 09:37:07 -0700 (PDT) In-Reply-To: <20141010154719.GA121201@msticlxl7.ims.intel.com> References: <20141006125527.GC13369@msticlxl57.ims.intel.com> <20141006141035.GZ1986@tucnak.redhat.com> <20141009121523.GB81768@msticlxl7.ims.intel.com> <20141009185105.GM1986@tucnak.redhat.com> <20141010154719.GA121201@msticlxl7.ims.intel.com> Date: Fri, 10 Oct 2014 16:39:00 -0000 Message-ID: Subject: Re: [PATCH i386 AVX512] [63.1/n] Add vpshufb, perm autogen (except for v64qi). From: Uros Bizjak To: Ilya Tocar Cc: Jakub Jelinek , Kirill Yukhin , Richard Henderson , GCC Patches Content-Type: text/plain; charset=UTF-8 X-SW-Source: 2014-10/txt/msg00974.txt.bz2 On Fri, Oct 10, 2014 at 5:47 PM, Ilya Tocar wrote: >> My strong preference would be: >> enum machine_mode maskmode = mode; >> rtx (*gen) (rtx, rtx, rtx, rtx); >> right below the enum machine_mode mode = GET_MODE (d ? d->op0 : op0); >> line and then inside of the first switch just do: >> ... >> case V16SImode: >> if (!TARGET_AVX512F) >> return false; >> gen = gen_avx512f_vpermi2varv16si3; >> break; >> case V4SFmode: >> if (!TARGET_AVX512VL) >> return false; >> gen = gen_avx512vl_vpermi2varv4sf3; >> maskmode = V4SImode; >> break; >> ... >> etc., then in the mask = line use: >> mask = gen_rtx_CONST_VECTOR (maskmode, gen_rtvec_v (d->nelt, vec)); >> and finally instead of the second switch do: >> emit_insn (gen (target, op0, force_reg (maskmode, mask), op1)); >> return true; >> > Updated patch below. Please recode that horrible first switch statement to: --cut here-- rtx (*gen) (rtx, rtx, rtx, rtx) = NULL; switch (mode) { case V8HImode: if (TARGET_AVX512VL && TARGET_AVX152BW) gen = gen_avx512vl_vpermi2varv8hi3; break; ... case V2DFmode: if (TARGET_AVX512VL) { gen = gen_avx512vl_vpermi2varv2df3; maskmode = V2DImode; } break; default: break; } if (gen == NULL) return false; --cut here-- The patch is OK with the above improvement. (Please also note that the patch has a bunch of i386.md changes that will clash with followup patch series). Thanks, Uros.