From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qk1-x72c.google.com (mail-qk1-x72c.google.com [IPv6:2607:f8b0:4864:20::72c]) by sourceware.org (Postfix) with ESMTPS id E72763893669 for ; Wed, 21 Jul 2021 08:23:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E72763893669 Received: by mail-qk1-x72c.google.com with SMTP id n10so1324106qke.12 for ; Wed, 21 Jul 2021 01:23:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=CD9slLkrGoackdp7wJPjWdOU7XsiyBLiWAm/WjwdMho=; b=UcSSbmh2oGJVOijAsJ7wr2mURzHz4dDoozXEoItX4VrwLa+ik1fYUFHQQDxoAtkVPC /TFtQV6ma4CIq6fHd52wx2X9XF8HFfjCB/t0lGEV9Lodg000FmqBW2SHEmgtVgjuNIaM RoZNG9zyBZg6diYYowfcxKu3GBNToAjaWrDh/PVtGI4Bkw3b+oLzp14MAwpEqkfaZB/q gxQrTtaBh2/W5/0osLl7X+7hD+1bqGQnssCSf6KomfZyUfTJgfu8OxUEyqzFAmOo0r4Z yy5Hft9o6Tea1ZhaQ2e1SiLT+Y/34uYGVYn7BgU0bwygnoW64o9qCSkPSH4UQ1yG/wsw E9RQ== X-Gm-Message-State: AOAM532QHiIrIhBW2G8TMlu7cumS8sCsbw8PDWOyYN49tqF4GtpVsQbv ECtkZsiosrXvy62BZRmgwBGdlVwNy5ThVz2FJAY= X-Google-Smtp-Source: ABdhPJxBi09MlxakgNIUVV8C7rTZXCZLMbHRVogg58lNNbvP/DnVlbkL0isQuo0Cw9xmUvb6jDOT2kNVG6emxtMPeQE= X-Received: by 2002:a05:620a:149c:: with SMTP id w28mr33921999qkj.127.1626855782565; Wed, 21 Jul 2021 01:23:02 -0700 (PDT) MIME-Version: 1.0 References: <20210720123314.79588-1-hongtao.liu@intel.com> In-Reply-To: From: Uros Bizjak Date: Wed, 21 Jul 2021 10:22:51 +0200 Message-ID: Subject: Re: [PATCH] Support logic shift left/right for avx512 mask type. To: Hongtao Liu Cc: liuhongt , "gcc-patches@gcc.gnu.org" , "H. J. Lu" , Richard Biener Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 21 Jul 2021 08:23:04 -0000 On Wed, Jul 21, 2021 at 5:05 AM Hongtao Liu wrote: > > On Tue, Jul 20, 2021 at 9:41 PM Uros Bizjak wrote: > > > > On Tue, Jul 20, 2021 at 2:33 PM liuhongt wrote: > > > > > > Hi: > > > As mention in https://gcc.gnu.org/pipermail/gcc-patches/2021-July/575420.html > > > > > > ----cut start----- > > > > note for the lowpart we can just view-convert away the excess bits, > > > > fully re-using the mask. We generate surprisingly "good" code: > > > > > > > > kmovb %k1, %edi > > > > shrb $4, %dil > > > > kmovb %edi, %k2 > > > > > > > > besides the lack of using kshiftrb. I guess we're just lacking > > > > a mask register alternative for > > > Yes, we can do it similar as kor/kand/kxor. > > > ---cut end-------- > > > > > > Bootstrap and regtested on x86_64-linux-gnu{-m32,}. > > > Ok for trunk? > > > > > > gcc/ChangeLog: > > > > > > * config/i386/constraints.md (Wb): New constraint. > > > (Ww): Ditto. > > > * config/i386/i386.md (*ashlhi3_1): Extend to avx512 mask > > > shift. > > > (*ashlqi3_1): Ditto. > > > (*3_1): Ditto. > > > (*3_1): Ditto. > > > * config/i386/sse.md (k): New define_split after > > > it to convert generic shift pattern to mask shift ones. > > > > > > gcc/testsuite/ChangeLog: > > > > > > * gcc.target/i386/mask-shift.c: New test. +(define_insn "*lshr3_1" + [(set (match_operand:SWI12 0 "nonimmediate_operand" "=m, ?k") + (lshiftrt:SWI12 + (match_operand:SWI12 1 "nonimmediate_operand" "0, k") + (match_operand:QI 2 "nonmemory_operand" "c, "))) + (clobber (reg:CC FLAGS_REG))] + "ix86_binary_operator_ok (LSHIFTRT, mode, operands)" Also split this one to QImode and HImode to avoid conditions in isa attribute. OK with this change. Thanks, Uros.