From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qt1-x82e.google.com (mail-qt1-x82e.google.com [IPv6:2607:f8b0:4864:20::82e]) by sourceware.org (Postfix) with ESMTPS id 1362A3858D32 for ; Wed, 15 Jun 2022 05:51:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 1362A3858D32 Received: by mail-qt1-x82e.google.com with SMTP id k18so7651269qtm.9 for ; Tue, 14 Jun 2022 22:51:41 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=GZ4J4QUV7BnRtV9icLByQAyZR0vNWVZnN4lcBB7OpeA=; b=n87oVgHVOx/HbcrQgrOGvnZVMRGP18Oao7W+PIPlCx+gAMfZD45CeDZveGPgleufcB m4aOJXvLn5Vnk6T03oJBVMpdH0ZTdmiWNEU4ZmG6AN1edzyQVUhZkChToQz/leBtDces pHitnfB4hlwrWWsfD+gjVAmXDB3jkNxcje/7glXDBB3njIhGHP4NRRdcm14iepxsjMjx Xp4T5NGJwp3xW0JnqgcVi39IsHUguZMEoVxoBuE/l0O0SvJ587rn8BuIBcYJ3/nnRN4I DcX4W15e6xqd41OPJQgpoV3oMyEzs+hm8s1AM4A3Dn4EIxRRmRkKOdo/s5w5y7+8OCfZ o2KQ== X-Gm-Message-State: AOAM531ZvthTLMOiciplmZ/5HMsg5I7hVRrqr093L1bSU++81gz7Z3wg 4urIRX+zqiOm8+GGEiwqTzoFBxpWep8Exh3uP6c= X-Google-Smtp-Source: ABdhPJwWXo2tTNMg28z4e3SHh5PZHXjPrj8ANuSzQzqJD/jAlPTrKAaN441TipchTxxqI+5orjclptMHZRRe6Sig0GE= X-Received: by 2002:a05:622a:5d4:b0:305:8ff:b558 with SMTP id d20-20020a05622a05d400b0030508ffb558mr7460874qtb.569.1655272300428; Tue, 14 Jun 2022 22:51:40 -0700 (PDT) MIME-Version: 1.0 References: <20220614224926.4779-1-hongtao.liu@intel.com> In-Reply-To: <20220614224926.4779-1-hongtao.liu@intel.com> From: Uros Bizjak Date: Wed, 15 Jun 2022 07:51:29 +0200 Message-ID: Subject: Re: [PATCH] Fix ICE in extract_insn, at recog.cc:2791 To: liuhongt Cc: "gcc-patches@gcc.gnu.org" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_NUMSUBJECT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, WEIRD_PORT autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 15 Jun 2022 05:51:42 -0000 On Wed, Jun 15, 2022 at 12:49 AM liuhongt wrote: > > (In reply to Uro=C5=A1 Bizjak from comment #1) > > Instruction does not accept memory operand for operand 3: > > > > (define_insn_and_split > > "*_blendv_ltint" > > [(set (match_operand: 0 "register_operand" "=3DYr,*x,x") > > (unspec: > > [(match_operand: 1 "register_operand" "0,0,x") > > (match_operand: 2 "vector_operand" "YrBm,*xBm,xm"= ) > > (subreg: > > (lt:VI48_AVX > > (match_operand:VI48_AVX 3 "register_operand" "Yz,Yz,x") > > (match_operand:VI48_AVX 4 "const0_operand")) 0)] > > UNSPEC_BLENDV))] > > > > The problematic insn is: > > > > (define_insn_and_split "*avx_cmp3_ltint_not" > > [(set (match_operand:VI48_AVX 0 "register_operand") > > (vec_merge:VI48_AVX > > (match_operand:VI48_AVX 1 "vector_operand") > > (match_operand:VI48_AVX 2 "vector_operand") > > (unspec: > > [(subreg:VI48_AVX > > (not: > > (match_operand: 3 "vector_operand")) 0) > > (match_operand:VI48_AVX 4 "const0_operand") > > (match_operand:SI 5 "const_0_to_7_operand")] > > UNSPEC_PCMP)))] > > > > which gets split to the above pattern. > > > > In the preparation statements we have: > > > > if (!MEM_P (operands[3])) > > operands[3] =3D force_reg (mode, operands[3]); > > operands[3] =3D lowpart_subreg (mode, operands[3], mode); > > > > Which won't fly when operand 3 is memory operand... > > > > Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. > Ok for trunk? > > gcc/ChangeLog: > > PR target/105953 > * config/i386/sse.md (*avx_cmp3_ltint_not): Force_reg > operands[3]. > > gcc/testsuite/ChangeLog: > > * g++.target/i386/pr105953.C: New test. LGTM. Thanks, Uros. > --- > gcc/config/i386/sse.md | 3 +-- > gcc/testsuite/g++.target/i386/pr105953.C | 4 ++++ > 2 files changed, 5 insertions(+), 2 deletions(-) > create mode 100644 gcc/testsuite/g++.target/i386/pr105953.C > > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md > index 75609eaf9b7..3e3d96fe087 100644 > --- a/gcc/config/i386/sse.md > +++ b/gcc/config/i386/sse.md > @@ -3643,8 +3643,7 @@ (define_insn_and_split "*avx_cmp3_ltint_not" > gen_lowpart (mode, operands[1])); > operands[2] =3D gen_lowpart (mode, operands[2]); > > - if (!MEM_P (operands[3])) > - operands[3] =3D force_reg (mode, operands[3]); > + operands[3] =3D force_reg (mode, operands[3]); > operands[3] =3D lowpart_subreg (mode, operands[3], = mode); > }) > > diff --git a/gcc/testsuite/g++.target/i386/pr105953.C b/gcc/testsuite/g++= .target/i386/pr105953.C > new file mode 100644 > index 00000000000..b423d2dfdae > --- /dev/null > +++ b/gcc/testsuite/g++.target/i386/pr105953.C > @@ -0,0 +1,4 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -mavx512vl -mabi=3Dms" } */ > + > +#include "pr100738-1.C" > -- > 2.18.1 >