From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw1-x112b.google.com (mail-yw1-x112b.google.com [IPv6:2607:f8b0:4864:20::112b]) by sourceware.org (Postfix) with ESMTPS id 4BCB6385742B for ; Thu, 27 Oct 2022 12:29:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 4BCB6385742B Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-yw1-x112b.google.com with SMTP id 00721157ae682-368edbc2c18so12163007b3.13 for ; Thu, 27 Oct 2022 05:29:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=TzJKOjD4rtpUWSyGHhHig2p0NOD6Xq5sPd+wUMo2sXI=; b=J4axhFI5efs2ET+xS0aUYdqObMtGmwDp3jCGOwrYCqoG7BxchdAeiuUtZujG7h/uV2 OGeY4LMjWnlJkNhsXv5ylUSwpu3hWHLW6n24rzzDw1+a7rnaVknhqEABjL+JfTVz72uJ 5LG/A1+Rk0Y4vrw/nPEwSvJiyw4TmbcSw1sIkLNCQbIBYly9y9Z3bN4I2t2eGrctMZCd OXEHwcaRNnZkHOEAdf+pk4eOGXAo8AAxHuHz0epNzvW6kdpozUWQb+J1VxJ5lmGO0xnu 3yyvGIZXVIAMN9qALlnUi4RRPoFUY78+Bmsekgq3++FP2caYGiIP63/sZ8lzFODxMeN2 owzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=TzJKOjD4rtpUWSyGHhHig2p0NOD6Xq5sPd+wUMo2sXI=; b=hCejRDDkGD0353IHLJLp9ELv77hvaEMLfyn6fWhyQ9IRkJdYANK4agzEagWGx9Vwav DiVR2ee9Jpv4htUE/HCCQR3dT17zTz8ct7FyhCdMU2/j9d1BTMHYdX12rCrKtpRB1Gzk 6+GNah80OvHjrrsDT0b+v/J5Y5oOMVIzsPRMxYHnoKX3mqknSc1C1ZeV7jWeOpPABNub cbGv5EF4ECTkV8BuMoLYRLL98uAhXqJiJQHL4rSyyFRsG/mjzFf2eD4mrfrx13lY659D j9H8QyJYEs9NGzItfYUun3Z+Fa1F9x3EfzWFA1AWWiV9lTiFk5RpTmRXU7pw54ZPFhAS bByg== X-Gm-Message-State: ACrzQf2UpSFcojveYlTJ3RtuAqnwiynDaLJ0hOUAtGxBBdHHPCMVATTH W0mJ1Z9MulbCzUtLmyrlP10tQzxxiq1j+xQB5H4= X-Google-Smtp-Source: AMsMyM7PoMz1xTVKOJhXsQhxEaoaSJ9y3MOq9kz62RICetkppZEOoljRCy6hBURWiR4lgcVgnYHfrTKPPBzO7Lm+oKs= X-Received: by 2002:a81:6208:0:b0:367:f222:df0d with SMTP id w8-20020a816208000000b00367f222df0dmr36087035ywb.422.1666873773431; Thu, 27 Oct 2022 05:29:33 -0700 (PDT) MIME-Version: 1.0 References: <20221027105354.3151191-1-hongtao.liu@intel.com> In-Reply-To: <20221027105354.3151191-1-hongtao.liu@intel.com> From: Uros Bizjak Date: Thu, 27 Oct 2022 14:29:22 +0200 Message-ID: Subject: Re: [PATCH] [x86] Fix incorrect digit constraint To: liuhongt Cc: gcc-patches@gcc.gnu.org, crazylht@gmail.com, hjl.tools@gmail.com Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, Oct 27, 2022 at 12:55 PM liuhongt wrote: > > Matching constraints are used in these circumstances. More precisely, > the two operands that match must include one input-only operand and > one output-only operand. Moreover, the digit must be a smaller number > than the number of the operand that uses it in the constraint. > > In pr107057, the 2 operands in the pattern are both input operands. Ouch... > Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. > Ok for trunk? You have a couple of other patterns where operand 1 is matched to produce vmovddup insn. These are *avx512f_unpcklpd512 and avx_unpcklpd256. You can also remove expander in both cases. Uros. > > gcc/ChangeLog: > > PR target/107057 > * config/i386/sse.md (*vec_interleave_highv2df): Remove > constraint 1. > (*vec_interleave_lowv2df): Ditto. > (vec_concatv2df): Ditto. > * config/i386/i386.cc (ix86_vec_interleave_v2df_operator_ok): > Disallow MEM_P (op1) && MEM_P (op2). > > gcc/testsuite/ChangeLog: > > * gcc.target/i386/pr107057.c: New test. > --- > gcc/config/i386/i386.cc | 2 +- > gcc/config/i386/sse.md | 68 +++++++++++------------- > gcc/testsuite/gcc.target/i386/pr107057.c | 19 +++++++ > 3 files changed, 50 insertions(+), 39 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/i386/pr107057.c > > diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc > index aeea26ef4be..e3b7bea0d68 100644 > --- a/gcc/config/i386/i386.cc > +++ b/gcc/config/i386/i386.cc > @@ -15652,7 +15652,7 @@ ix86_vec_interleave_v2df_operator_ok (rtx operands[3], bool high) > if (MEM_P (operands[0])) > return rtx_equal_p (operands[0], operands[1 + high]); > if (MEM_P (operands[1]) && MEM_P (operands[2])) > - return TARGET_SSE3 && rtx_equal_p (operands[1], operands[2]); > + return false; > return true; > } > > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md > index f4b5506703f..e6fefe39ca2 100644 > --- a/gcc/config/i386/sse.md > +++ b/gcc/config/i386/sse.md > @@ -12170,29 +12170,28 @@ (define_expand "vec_interleave_highv2df" > }) > > (define_insn "*vec_interleave_highv2df" > - [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,v,v,x,v,m") > + [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,v,x,v,m") > (vec_select:V2DF > (vec_concat:V4DF > - (match_operand:V2DF 1 "nonimmediate_operand" " 0,v,o,o,o,v") > - (match_operand:V2DF 2 "nonimmediate_operand" " x,v,1,0,v,0")) > + (match_operand:V2DF 1 "nonimmediate_operand" " 0,v,o,o,v") > + (match_operand:V2DF 2 "nonimmediate_operand" " x,v,0,v,0")) > (parallel [(const_int 1) > (const_int 3)])))] > "TARGET_SSE2 && ix86_vec_interleave_v2df_operator_ok (operands, 1)" > "@ > unpckhpd\t{%2, %0|%0, %2} > vunpckhpd\t{%2, %1, %0|%0, %1, %2} > - %vmovddup\t{%H1, %0|%0, %H1} > movlpd\t{%H1, %0|%0, %H1} > vmovlpd\t{%H1, %2, %0|%0, %2, %H1} > %vmovhpd\t{%1, %0|%q0, %1}" > - [(set_attr "isa" "noavx,avx,sse3,noavx,avx,*") > - (set_attr "type" "sselog,sselog,sselog,ssemov,ssemov,ssemov") > + [(set_attr "isa" "noavx,avx,noavx,avx,*") > + (set_attr "type" "sselog,sselog,ssemov,ssemov,ssemov") > (set (attr "prefix_data16") > - (if_then_else (eq_attr "alternative" "3,5") > + (if_then_else (eq_attr "alternative" "2,4") > (const_string "1") > (const_string "*"))) > - (set_attr "prefix" "orig,maybe_evex,maybe_vex,orig,maybe_evex,maybe_vex") > - (set_attr "mode" "V2DF,V2DF,DF,V1DF,V1DF,V1DF")]) > + (set_attr "prefix" "orig,maybe_evex,orig,maybe_evex,maybe_vex") > + (set_attr "mode" "V2DF,V2DF,V1DF,V1DF,V1DF")]) > > (define_expand "avx512f_movddup512" > [(set (match_operand:V8DF 0 "register_operand") > @@ -12332,29 +12331,28 @@ (define_expand "vec_interleave_lowv2df" > }) > > (define_insn "*vec_interleave_lowv2df" > - [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,v,v,x,v,o") > + [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,v,x,v,o") > (vec_select:V2DF > (vec_concat:V4DF > - (match_operand:V2DF 1 "nonimmediate_operand" " 0,v,m,0,v,0") > - (match_operand:V2DF 2 "nonimmediate_operand" " x,v,1,m,m,v")) > + (match_operand:V2DF 1 "nonimmediate_operand" " 0,v,0,v,0") > + (match_operand:V2DF 2 "nonimmediate_operand" " x,v,m,m,v")) > (parallel [(const_int 0) > (const_int 2)])))] > "TARGET_SSE2 && ix86_vec_interleave_v2df_operator_ok (operands, 0)" > "@ > unpcklpd\t{%2, %0|%0, %2} > vunpcklpd\t{%2, %1, %0|%0, %1, %2} > - %vmovddup\t{%1, %0|%0, %q1} > movhpd\t{%2, %0|%0, %q2} > vmovhpd\t{%2, %1, %0|%0, %1, %q2} > %vmovlpd\t{%2, %H0|%H0, %2}" > - [(set_attr "isa" "noavx,avx,sse3,noavx,avx,*") > - (set_attr "type" "sselog,sselog,sselog,ssemov,ssemov,ssemov") > + [(set_attr "isa" "noavx,avx,noavx,avx,*") > + (set_attr "type" "sselog,sselog,ssemov,ssemov,ssemov") > (set (attr "prefix_data16") > - (if_then_else (eq_attr "alternative" "3,5") > + (if_then_else (eq_attr "alternative" "2,4") > (const_string "1") > (const_string "*"))) > - (set_attr "prefix" "orig,maybe_evex,maybe_vex,orig,maybe_evex,maybe_vex") > - (set_attr "mode" "V2DF,V2DF,DF,V1DF,V1DF,V1DF")]) > + (set_attr "prefix" "orig,maybe_evex,orig,maybe_evex,maybe_vex") > + (set_attr "mode" "V2DF,V2DF,V1DF,V1DF,V1DF")]) > > (define_split > [(set (match_operand:V2DF 0 "memory_operand") > @@ -13560,56 +13558,50 @@ (define_insn "vec_dupv2df" > (set_attr "mode" "V2DF,DF,DF")]) > > (define_insn "vec_concatv2df" > - [(set (match_operand:V2DF 0 "register_operand" "=x,x,v,x,v,x,x, v,x,x") > + [(set (match_operand:V2DF 0 "register_operand" "=x,x,v,x,x, v,x,x") > (vec_concat:V2DF > - (match_operand:DF 1 "nonimmediate_operand" " 0,x,v,m,m,0,x,vm,0,0") > - (match_operand:DF 2 "nonimm_or_0_operand" " x,x,v,1,1,m,m, C,x,m")))] > - "TARGET_SSE > - && (!(MEM_P (operands[1]) && MEM_P (operands[2])) > - || (TARGET_SSE3 && rtx_equal_p (operands[1], operands[2])))" > + (match_operand:DF 1 "nonimmediate_operand" " 0,x,v,0,x,vm,0,0") > + (match_operand:DF 2 "nonimm_or_0_operand" " x,x,v,m,m, C,x,m")))] > + "TARGET_SSE && !(MEM_P (operands[1]) && MEM_P (operands[2]))" > "@ > unpcklpd\t{%2, %0|%0, %2} > vunpcklpd\t{%2, %1, %0|%0, %1, %2} > vunpcklpd\t{%2, %1, %0|%0, %1, %2} > - %vmovddup\t{%1, %0|%0, %1} > - vmovddup\t{%1, %0|%0, %1} > movhpd\t{%2, %0|%0, %2} > vmovhpd\t{%2, %1, %0|%0, %1, %2} > %vmovq\t{%1, %0|%0, %1} > movlhps\t{%2, %0|%0, %2} > movhps\t{%2, %0|%0, %2}" > [(set (attr "isa") > - (cond [(eq_attr "alternative" "0,5") > + (cond [(eq_attr "alternative" "0,3") > (const_string "sse2_noavx") > - (eq_attr "alternative" "1,6") > + (eq_attr "alternative" "1,4") > (const_string "avx") > - (eq_attr "alternative" "2,4") > + (eq_attr "alternative" "2") > (const_string "avx512vl") > - (eq_attr "alternative" "3") > - (const_string "sse3") > - (eq_attr "alternative" "7") > + (eq_attr "alternative" "5") > (const_string "sse2") > ] > (const_string "noavx"))) > (set (attr "type") > (if_then_else > - (eq_attr "alternative" "0,1,2,3,4") > + (eq_attr "alternative" "0,1,2") > (const_string "sselog") > (const_string "ssemov"))) > (set (attr "prefix_data16") > - (if_then_else (eq_attr "alternative" "5") > + (if_then_else (eq_attr "alternative" "3") > (const_string "1") > (const_string "*"))) > (set (attr "prefix") > - (cond [(eq_attr "alternative" "1,6") > + (cond [(eq_attr "alternative" "1,4") > (const_string "vex") > - (eq_attr "alternative" "2,4") > + (eq_attr "alternative" "2") > (const_string "evex") > - (eq_attr "alternative" "3,7") > + (eq_attr "alternative" "5") > (const_string "maybe_vex") > ] > (const_string "orig"))) > - (set_attr "mode" "V2DF,V2DF,V2DF, DF, DF, V1DF,V1DF,DF,V4SF,V2SF")]) > + (set_attr "mode" "V2DF,V2DF,V2DF,V1DF,V1DF,DF,V4SF,V2SF")]) > > ;; vmovq clears also the higher bits. > (define_insn "vec_set_0" > diff --git a/gcc/testsuite/gcc.target/i386/pr107057.c b/gcc/testsuite/gcc.target/i386/pr107057.c > new file mode 100644 > index 00000000000..40b49ac21ec > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/pr107057.c > @@ -0,0 +1,19 @@ > +/* { dg-do compile { target { ! ia32 } } } */ > +/* { dg-options "-mavx -mcmodel=large -O3" } */ > + > +typedef double v2df __attribute__ ((vector_size (16))); > +v2df f (double a, double b) > +{ > + v2df v; > + double *c = (double *)&v; > + *c = a; > + *(c+1) = b; > + return v; > +} > +void g () > +{ > + v2df x = f (1.0, 1.0); > + v2df y = f (2.0, 2.0); > + for (;*(double *)&x<=8; x+=y) > + g (); > +} > -- > 2.27.0 >