* [PATCH] Expand __builtin_memcmp_eq with ptest for OI/TImode.
@ 2022-05-05 7:37 liuhongt
2022-05-05 7:37 ` Hongtao Liu
2022-05-05 7:49 ` Richard Biener
0 siblings, 2 replies; 14+ messages in thread
From: liuhongt @ 2022-05-05 7:37 UTC (permalink / raw)
To: gcc-patches
Enable optimization for TImode only under 32-bit target, for 64-bit
target there could be extra ineteger <-> sse move regarding psABI,
not efficient.
Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}
Ok for trunk?
gcc/ChangeLog:
PR target/104610
* config/i386/i386-expand.cc (ix86_expand_branch): Use ptest
for TI/QImode when code is EQ or NE.
* config/i386/i386.md (SDWIM1248): New iterator.
(cbranch<mode>4): Split TImode into a separate expander.
(cbranchti4): New expander.
* config/i386/predicates.md (timode_comparison_operator): New
predicate.
* config/i386/sse.md (cbranch<mode>4): Extend to OImode.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr104610.c: New test.
---
gcc/config/i386/i386-expand.cc | 13 +++++++++++-
gcc/config/i386/i386.md | 27 ++++++++++++++++++++++--
gcc/config/i386/predicates.md | 6 ++++++
gcc/config/i386/sse.md | 10 +++++++--
gcc/testsuite/gcc.target/i386/pr104610.c | 23 ++++++++++++++++++++
5 files changed, 74 insertions(+), 5 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/i386/pr104610.c
diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index bc806ffa283..a2012a158ae 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -2264,13 +2264,24 @@ ix86_expand_branch (enum rtx_code code, rtx op0, rtx op1, rtx label)
{
machine_mode mode = GET_MODE (op0);
rtx tmp;
+ machine_mode p_mode = GET_MODE_SIZE (mode) == 32 ? V4DImode : V2DImode;
+ /* Using ptest for TImode only for 32-bit target since it's splitted into
+ 4 comparisons. For 64-bit target there could be extra ineteger <-> sse
+ move regarding psABI, not efficient. */
+ if ((code == EQ || code == NE)
+ && ((mode == OImode && TARGET_AVX)
+ || (mode == TImode && !TARGET_64BIT && TARGET_SSE4_1)))
+ {
+ op0 = lowpart_subreg (p_mode, force_reg (mode, op0), mode);
+ op1 = lowpart_subreg (p_mode, force_reg (mode, op1), mode);
+ mode = p_mode;
+ }
/* Handle special case - vector comparsion with boolean result, transform
it using ptest instruction. */
if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
{
rtx flag = gen_rtx_REG (CCZmode, FLAGS_REG);
- machine_mode p_mode = GET_MODE_SIZE (mode) == 32 ? V4DImode : V2DImode;
gcc_assert (code == EQ || code == NE);
/* Generate XOR since we can't check that one operand is zero vector. */
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index b321cda1f22..f91325015c9 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -1069,6 +1069,10 @@ (define_mode_iterator SDWIM [(QI "TARGET_QIMODE_MATH")
(HI "TARGET_HIMODE_MATH")
SI DI (TI "TARGET_64BIT")])
+(define_mode_iterator SDWIM1248 [(QI "TARGET_QIMODE_MATH")
+ (HI "TARGET_HIMODE_MATH")
+ SI DI])
+
;; Math-dependant single word integer modes.
(define_mode_iterator SWIM [(QI "TARGET_QIMODE_MATH")
(HI "TARGET_HIMODE_MATH")
@@ -1322,8 +1326,8 @@ (define_mode_iterator PTR
(define_expand "cbranch<mode>4"
[(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand:SDWIM 1 "nonimmediate_operand")
- (match_operand:SDWIM 2 "<general_operand>")))
+ (compare:CC (match_operand:SDWIM1248 1 "nonimmediate_operand")
+ (match_operand:SDWIM1248 2 "<general_operand>")))
(set (pc) (if_then_else
(match_operator 0 "ordered_comparison_operator"
[(reg:CC FLAGS_REG) (const_int 0)])
@@ -1338,6 +1342,25 @@ (define_expand "cbranch<mode>4"
DONE;
})
+(define_expand "cbranchti4"
+ [(set (reg:CC FLAGS_REG)
+ (compare:CC (match_operand:TI 1 "nonimmediate_operand")
+ (match_operand:TI 2 "x86_64_general_operand")))
+ (set (pc) (if_then_else
+ (match_operator 0 "timode_comparison_operator"
+ [(reg:CC FLAGS_REG) (const_int 0)])
+ (label_ref (match_operand 3))
+ (pc)))]
+ "TARGET_64BIT || TARGET_SSE4_1"
+{
+ if (MEM_P (operands[1]) && MEM_P (operands[2]))
+ operands[1] = force_reg (TImode, operands[1]);
+
+ ix86_expand_branch (GET_CODE (operands[0]),
+ operands[1], operands[2], operands[3]);
+ DONE;
+})
+
(define_expand "cstore<mode>4"
[(set (reg:CC FLAGS_REG)
(compare:CC (match_operand:SWIM 2 "nonimmediate_operand")
diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
index a8cc17a054d..fb3be3a262f 100644
--- a/gcc/config/i386/predicates.md
+++ b/gcc/config/i386/predicates.md
@@ -1414,6 +1414,12 @@ (define_predicate "ix86_comparison_uns_operator"
(define_predicate "bt_comparison_operator"
(match_code "ne,eq"))
+(define_predicate "timode_comparison_operator"
+ (ior (and (match_test "TARGET_SSE4_1")
+ (match_operand 0 "bt_comparison_operator"))
+ (and (match_test "TARGET_64BIT")
+ (match_operand 0 "ordered_comparison_operator"))))
+
(define_predicate "shr_comparison_operator"
(match_code "gtu,leu"))
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 7b791def542..0d194cee769 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -26034,10 +26034,14 @@ (define_expand "maskstore<mode><avx512fmaskmodelower>"
(match_operand:<avx512fmaskmode> 2 "register_operand")))]
"TARGET_AVX512BW")
+(define_mode_iterator VI48_OI_AVX
+ [(V8SI "TARGET_AVX") (V4DI "TARGET_AVX") (OI "TARGET_AVX")
+ V4SI V2DI])
+
(define_expand "cbranch<mode>4"
[(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand:VI48_AVX 1 "register_operand")
- (match_operand:VI48_AVX 2 "nonimmediate_operand")))
+ (compare:CC (match_operand:VI48_OI_AVX 1 "register_operand")
+ (match_operand:VI48_OI_AVX 2 "nonimmediate_operand")))
(set (pc) (if_then_else
(match_operator 0 "bt_comparison_operator"
[(reg:CC FLAGS_REG) (const_int 0)])
@@ -26045,6 +26049,8 @@ (define_expand "cbranch<mode>4"
(pc)))]
"TARGET_SSE4_1"
{
+ if (!vector_operand (operands[2], <MODE>mode))
+ operands[2] = force_reg (<MODE>mode, operands[2]);
ix86_expand_branch (GET_CODE (operands[0]),
operands[1], operands[2], operands[3]);
DONE;
diff --git a/gcc/testsuite/gcc.target/i386/pr104610.c b/gcc/testsuite/gcc.target/i386/pr104610.c
new file mode 100644
index 00000000000..68f548594fd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr104610.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mmove-max=256 -mstore-max=256" } */
+/* { dg-final { scan-assembler-times {(?n)ptest.*xmm} 1 { target ia32 } } } */
+/* { dg-final { scan-assembler-times {(?n)vptest.*ymm} 1 } } */
+/* { dg-final { scan-assembler-times {sete} 2 } } */
+/* { dg-final { scan-assembler-not {(?n)je.*L[0-9]} } } */
+/* { dg-final { scan-assembler-not {(?n)jne.*L[0-9]} } } */
+
+
+#include<stdbool.h>
+__attribute__((target("sse4.1")))
+bool f128(char *a)
+{
+ char t[] = "012345678901234";
+ return __builtin_memcmp(a, &t[0], sizeof(t)) == 0;
+}
+
+__attribute__((target("avx")))
+bool f256(char *a)
+{
+ char t[] = "0123456789012345678901234567890";
+ return __builtin_memcmp(a, &t[0], sizeof(t)) == 0;
+}
--
2.18.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] Expand __builtin_memcmp_eq with ptest for OI/TImode.
2022-05-05 7:37 [PATCH] Expand __builtin_memcmp_eq with ptest for OI/TImode liuhongt
@ 2022-05-05 7:37 ` Hongtao Liu
2022-05-05 7:49 ` Richard Biener
1 sibling, 0 replies; 14+ messages in thread
From: Hongtao Liu @ 2022-05-05 7:37 UTC (permalink / raw)
To: Uros Bizjak; +Cc: GCC Patches, H. J. Lu
On Thu, May 5, 2022 at 3:37 PM liuhongt <hongtao.liu@intel.com> wrote:
>
> Enable optimization for TImode only under 32-bit target, for 64-bit
> target there could be extra ineteger <-> sse move regarding psABI,
> not efficient.
>
> Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}
> Ok for trunk?
>
> gcc/ChangeLog:
>
> PR target/104610
> * config/i386/i386-expand.cc (ix86_expand_branch): Use ptest
> for TI/QImode when code is EQ or NE.
> * config/i386/i386.md (SDWIM1248): New iterator.
> (cbranch<mode>4): Split TImode into a separate expander.
> (cbranchti4): New expander.
> * config/i386/predicates.md (timode_comparison_operator): New
> predicate.
> * config/i386/sse.md (cbranch<mode>4): Extend to OImode.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/i386/pr104610.c: New test.
> ---
> gcc/config/i386/i386-expand.cc | 13 +++++++++++-
> gcc/config/i386/i386.md | 27 ++++++++++++++++++++++--
> gcc/config/i386/predicates.md | 6 ++++++
> gcc/config/i386/sse.md | 10 +++++++--
> gcc/testsuite/gcc.target/i386/pr104610.c | 23 ++++++++++++++++++++
> 5 files changed, 74 insertions(+), 5 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/i386/pr104610.c
>
> diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
> index bc806ffa283..a2012a158ae 100644
> --- a/gcc/config/i386/i386-expand.cc
> +++ b/gcc/config/i386/i386-expand.cc
> @@ -2264,13 +2264,24 @@ ix86_expand_branch (enum rtx_code code, rtx op0, rtx op1, rtx label)
> {
> machine_mode mode = GET_MODE (op0);
> rtx tmp;
> + machine_mode p_mode = GET_MODE_SIZE (mode) == 32 ? V4DImode : V2DImode;
> + /* Using ptest for TImode only for 32-bit target since it's splitted into
> + 4 comparisons. For 64-bit target there could be extra ineteger <-> sse
> + move regarding psABI, not efficient. */
> + if ((code == EQ || code == NE)
> + && ((mode == OImode && TARGET_AVX)
> + || (mode == TImode && !TARGET_64BIT && TARGET_SSE4_1)))
> + {
> + op0 = lowpart_subreg (p_mode, force_reg (mode, op0), mode);
> + op1 = lowpart_subreg (p_mode, force_reg (mode, op1), mode);
> + mode = p_mode;
> + }
>
> /* Handle special case - vector comparsion with boolean result, transform
> it using ptest instruction. */
> if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
> {
> rtx flag = gen_rtx_REG (CCZmode, FLAGS_REG);
> - machine_mode p_mode = GET_MODE_SIZE (mode) == 32 ? V4DImode : V2DImode;
>
> gcc_assert (code == EQ || code == NE);
> /* Generate XOR since we can't check that one operand is zero vector. */
> diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
> index b321cda1f22..f91325015c9 100644
> --- a/gcc/config/i386/i386.md
> +++ b/gcc/config/i386/i386.md
> @@ -1069,6 +1069,10 @@ (define_mode_iterator SDWIM [(QI "TARGET_QIMODE_MATH")
> (HI "TARGET_HIMODE_MATH")
> SI DI (TI "TARGET_64BIT")])
>
> +(define_mode_iterator SDWIM1248 [(QI "TARGET_QIMODE_MATH")
> + (HI "TARGET_HIMODE_MATH")
> + SI DI])
> +
> ;; Math-dependant single word integer modes.
> (define_mode_iterator SWIM [(QI "TARGET_QIMODE_MATH")
> (HI "TARGET_HIMODE_MATH")
> @@ -1322,8 +1326,8 @@ (define_mode_iterator PTR
>
> (define_expand "cbranch<mode>4"
> [(set (reg:CC FLAGS_REG)
> - (compare:CC (match_operand:SDWIM 1 "nonimmediate_operand")
> - (match_operand:SDWIM 2 "<general_operand>")))
> + (compare:CC (match_operand:SDWIM1248 1 "nonimmediate_operand")
> + (match_operand:SDWIM1248 2 "<general_operand>")))
> (set (pc) (if_then_else
> (match_operator 0 "ordered_comparison_operator"
> [(reg:CC FLAGS_REG) (const_int 0)])
> @@ -1338,6 +1342,25 @@ (define_expand "cbranch<mode>4"
> DONE;
> })
>
> +(define_expand "cbranchti4"
> + [(set (reg:CC FLAGS_REG)
> + (compare:CC (match_operand:TI 1 "nonimmediate_operand")
> + (match_operand:TI 2 "x86_64_general_operand")))
> + (set (pc) (if_then_else
> + (match_operator 0 "timode_comparison_operator"
> + [(reg:CC FLAGS_REG) (const_int 0)])
> + (label_ref (match_operand 3))
> + (pc)))]
> + "TARGET_64BIT || TARGET_SSE4_1"
> +{
> + if (MEM_P (operands[1]) && MEM_P (operands[2]))
> + operands[1] = force_reg (TImode, operands[1]);
> +
> + ix86_expand_branch (GET_CODE (operands[0]),
> + operands[1], operands[2], operands[3]);
> + DONE;
> +})
> +
> (define_expand "cstore<mode>4"
> [(set (reg:CC FLAGS_REG)
> (compare:CC (match_operand:SWIM 2 "nonimmediate_operand")
> diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
> index a8cc17a054d..fb3be3a262f 100644
> --- a/gcc/config/i386/predicates.md
> +++ b/gcc/config/i386/predicates.md
> @@ -1414,6 +1414,12 @@ (define_predicate "ix86_comparison_uns_operator"
> (define_predicate "bt_comparison_operator"
> (match_code "ne,eq"))
>
> +(define_predicate "timode_comparison_operator"
> + (ior (and (match_test "TARGET_SSE4_1")
> + (match_operand 0 "bt_comparison_operator"))
> + (and (match_test "TARGET_64BIT")
> + (match_operand 0 "ordered_comparison_operator"))))
> +
> (define_predicate "shr_comparison_operator"
> (match_code "gtu,leu"))
>
> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> index 7b791def542..0d194cee769 100644
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -26034,10 +26034,14 @@ (define_expand "maskstore<mode><avx512fmaskmodelower>"
> (match_operand:<avx512fmaskmode> 2 "register_operand")))]
> "TARGET_AVX512BW")
>
> +(define_mode_iterator VI48_OI_AVX
> + [(V8SI "TARGET_AVX") (V4DI "TARGET_AVX") (OI "TARGET_AVX")
> + V4SI V2DI])
> +
> (define_expand "cbranch<mode>4"
> [(set (reg:CC FLAGS_REG)
> - (compare:CC (match_operand:VI48_AVX 1 "register_operand")
> - (match_operand:VI48_AVX 2 "nonimmediate_operand")))
> + (compare:CC (match_operand:VI48_OI_AVX 1 "register_operand")
> + (match_operand:VI48_OI_AVX 2 "nonimmediate_operand")))
> (set (pc) (if_then_else
> (match_operator 0 "bt_comparison_operator"
> [(reg:CC FLAGS_REG) (const_int 0)])
> @@ -26045,6 +26049,8 @@ (define_expand "cbranch<mode>4"
> (pc)))]
> "TARGET_SSE4_1"
> {
> + if (!vector_operand (operands[2], <MODE>mode))
> + operands[2] = force_reg (<MODE>mode, operands[2]);
> ix86_expand_branch (GET_CODE (operands[0]),
> operands[1], operands[2], operands[3]);
> DONE;
> diff --git a/gcc/testsuite/gcc.target/i386/pr104610.c b/gcc/testsuite/gcc.target/i386/pr104610.c
> new file mode 100644
> index 00000000000..68f548594fd
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr104610.c
> @@ -0,0 +1,23 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -mmove-max=256 -mstore-max=256" } */
> +/* { dg-final { scan-assembler-times {(?n)ptest.*xmm} 1 { target ia32 } } } */
> +/* { dg-final { scan-assembler-times {(?n)vptest.*ymm} 1 } } */
> +/* { dg-final { scan-assembler-times {sete} 2 } } */
> +/* { dg-final { scan-assembler-not {(?n)je.*L[0-9]} } } */
> +/* { dg-final { scan-assembler-not {(?n)jne.*L[0-9]} } } */
> +
> +
> +#include<stdbool.h>
> +__attribute__((target("sse4.1")))
> +bool f128(char *a)
> +{
> + char t[] = "012345678901234";
> + return __builtin_memcmp(a, &t[0], sizeof(t)) == 0;
> +}
> +
> +__attribute__((target("avx")))
> +bool f256(char *a)
> +{
> + char t[] = "0123456789012345678901234567890";
> + return __builtin_memcmp(a, &t[0], sizeof(t)) == 0;
> +}
> --
> 2.18.1
>
--
BR,
Hongtao
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] Expand __builtin_memcmp_eq with ptest for OI/TImode.
2022-05-05 7:37 [PATCH] Expand __builtin_memcmp_eq with ptest for OI/TImode liuhongt
2022-05-05 7:37 ` Hongtao Liu
@ 2022-05-05 7:49 ` Richard Biener
2022-05-05 8:08 ` Uros Bizjak
1 sibling, 1 reply; 14+ messages in thread
From: Richard Biener @ 2022-05-05 7:49 UTC (permalink / raw)
To: liuhongt; +Cc: GCC Patches
On Thu, May 5, 2022 at 9:37 AM liuhongt via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> Enable optimization for TImode only under 32-bit target, for 64-bit
> target there could be extra ineteger <-> sse move regarding psABI,
> not efficient.
>
> Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}
> Ok for trunk?
I wonder if this is better done in STV where we could assess this extra cost?
> gcc/ChangeLog:
>
> PR target/104610
> * config/i386/i386-expand.cc (ix86_expand_branch): Use ptest
> for TI/QImode when code is EQ or NE.
> * config/i386/i386.md (SDWIM1248): New iterator.
> (cbranch<mode>4): Split TImode into a separate expander.
> (cbranchti4): New expander.
> * config/i386/predicates.md (timode_comparison_operator): New
> predicate.
> * config/i386/sse.md (cbranch<mode>4): Extend to OImode.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/i386/pr104610.c: New test.
> ---
> gcc/config/i386/i386-expand.cc | 13 +++++++++++-
> gcc/config/i386/i386.md | 27 ++++++++++++++++++++++--
> gcc/config/i386/predicates.md | 6 ++++++
> gcc/config/i386/sse.md | 10 +++++++--
> gcc/testsuite/gcc.target/i386/pr104610.c | 23 ++++++++++++++++++++
> 5 files changed, 74 insertions(+), 5 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/i386/pr104610.c
>
> diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
> index bc806ffa283..a2012a158ae 100644
> --- a/gcc/config/i386/i386-expand.cc
> +++ b/gcc/config/i386/i386-expand.cc
> @@ -2264,13 +2264,24 @@ ix86_expand_branch (enum rtx_code code, rtx op0, rtx op1, rtx label)
> {
> machine_mode mode = GET_MODE (op0);
> rtx tmp;
> + machine_mode p_mode = GET_MODE_SIZE (mode) == 32 ? V4DImode : V2DImode;
> + /* Using ptest for TImode only for 32-bit target since it's splitted into
> + 4 comparisons. For 64-bit target there could be extra ineteger <-> sse
> + move regarding psABI, not efficient. */
> + if ((code == EQ || code == NE)
> + && ((mode == OImode && TARGET_AVX)
> + || (mode == TImode && !TARGET_64BIT && TARGET_SSE4_1)))
> + {
> + op0 = lowpart_subreg (p_mode, force_reg (mode, op0), mode);
> + op1 = lowpart_subreg (p_mode, force_reg (mode, op1), mode);
> + mode = p_mode;
> + }
>
> /* Handle special case - vector comparsion with boolean result, transform
> it using ptest instruction. */
> if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
> {
> rtx flag = gen_rtx_REG (CCZmode, FLAGS_REG);
> - machine_mode p_mode = GET_MODE_SIZE (mode) == 32 ? V4DImode : V2DImode;
>
> gcc_assert (code == EQ || code == NE);
> /* Generate XOR since we can't check that one operand is zero vector. */
> diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
> index b321cda1f22..f91325015c9 100644
> --- a/gcc/config/i386/i386.md
> +++ b/gcc/config/i386/i386.md
> @@ -1069,6 +1069,10 @@ (define_mode_iterator SDWIM [(QI "TARGET_QIMODE_MATH")
> (HI "TARGET_HIMODE_MATH")
> SI DI (TI "TARGET_64BIT")])
>
> +(define_mode_iterator SDWIM1248 [(QI "TARGET_QIMODE_MATH")
> + (HI "TARGET_HIMODE_MATH")
> + SI DI])
> +
> ;; Math-dependant single word integer modes.
> (define_mode_iterator SWIM [(QI "TARGET_QIMODE_MATH")
> (HI "TARGET_HIMODE_MATH")
> @@ -1322,8 +1326,8 @@ (define_mode_iterator PTR
>
> (define_expand "cbranch<mode>4"
> [(set (reg:CC FLAGS_REG)
> - (compare:CC (match_operand:SDWIM 1 "nonimmediate_operand")
> - (match_operand:SDWIM 2 "<general_operand>")))
> + (compare:CC (match_operand:SDWIM1248 1 "nonimmediate_operand")
> + (match_operand:SDWIM1248 2 "<general_operand>")))
> (set (pc) (if_then_else
> (match_operator 0 "ordered_comparison_operator"
> [(reg:CC FLAGS_REG) (const_int 0)])
> @@ -1338,6 +1342,25 @@ (define_expand "cbranch<mode>4"
> DONE;
> })
>
> +(define_expand "cbranchti4"
> + [(set (reg:CC FLAGS_REG)
> + (compare:CC (match_operand:TI 1 "nonimmediate_operand")
> + (match_operand:TI 2 "x86_64_general_operand")))
> + (set (pc) (if_then_else
> + (match_operator 0 "timode_comparison_operator"
> + [(reg:CC FLAGS_REG) (const_int 0)])
> + (label_ref (match_operand 3))
> + (pc)))]
> + "TARGET_64BIT || TARGET_SSE4_1"
> +{
> + if (MEM_P (operands[1]) && MEM_P (operands[2]))
> + operands[1] = force_reg (TImode, operands[1]);
> +
> + ix86_expand_branch (GET_CODE (operands[0]),
> + operands[1], operands[2], operands[3]);
> + DONE;
> +})
> +
> (define_expand "cstore<mode>4"
> [(set (reg:CC FLAGS_REG)
> (compare:CC (match_operand:SWIM 2 "nonimmediate_operand")
> diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
> index a8cc17a054d..fb3be3a262f 100644
> --- a/gcc/config/i386/predicates.md
> +++ b/gcc/config/i386/predicates.md
> @@ -1414,6 +1414,12 @@ (define_predicate "ix86_comparison_uns_operator"
> (define_predicate "bt_comparison_operator"
> (match_code "ne,eq"))
>
> +(define_predicate "timode_comparison_operator"
> + (ior (and (match_test "TARGET_SSE4_1")
> + (match_operand 0 "bt_comparison_operator"))
> + (and (match_test "TARGET_64BIT")
> + (match_operand 0 "ordered_comparison_operator"))))
> +
> (define_predicate "shr_comparison_operator"
> (match_code "gtu,leu"))
>
> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> index 7b791def542..0d194cee769 100644
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -26034,10 +26034,14 @@ (define_expand "maskstore<mode><avx512fmaskmodelower>"
> (match_operand:<avx512fmaskmode> 2 "register_operand")))]
> "TARGET_AVX512BW")
>
> +(define_mode_iterator VI48_OI_AVX
> + [(V8SI "TARGET_AVX") (V4DI "TARGET_AVX") (OI "TARGET_AVX")
> + V4SI V2DI])
> +
> (define_expand "cbranch<mode>4"
> [(set (reg:CC FLAGS_REG)
> - (compare:CC (match_operand:VI48_AVX 1 "register_operand")
> - (match_operand:VI48_AVX 2 "nonimmediate_operand")))
> + (compare:CC (match_operand:VI48_OI_AVX 1 "register_operand")
> + (match_operand:VI48_OI_AVX 2 "nonimmediate_operand")))
> (set (pc) (if_then_else
> (match_operator 0 "bt_comparison_operator"
> [(reg:CC FLAGS_REG) (const_int 0)])
> @@ -26045,6 +26049,8 @@ (define_expand "cbranch<mode>4"
> (pc)))]
> "TARGET_SSE4_1"
> {
> + if (!vector_operand (operands[2], <MODE>mode))
> + operands[2] = force_reg (<MODE>mode, operands[2]);
> ix86_expand_branch (GET_CODE (operands[0]),
> operands[1], operands[2], operands[3]);
> DONE;
> diff --git a/gcc/testsuite/gcc.target/i386/pr104610.c b/gcc/testsuite/gcc.target/i386/pr104610.c
> new file mode 100644
> index 00000000000..68f548594fd
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr104610.c
> @@ -0,0 +1,23 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -mmove-max=256 -mstore-max=256" } */
> +/* { dg-final { scan-assembler-times {(?n)ptest.*xmm} 1 { target ia32 } } } */
> +/* { dg-final { scan-assembler-times {(?n)vptest.*ymm} 1 } } */
> +/* { dg-final { scan-assembler-times {sete} 2 } } */
> +/* { dg-final { scan-assembler-not {(?n)je.*L[0-9]} } } */
> +/* { dg-final { scan-assembler-not {(?n)jne.*L[0-9]} } } */
> +
> +
> +#include<stdbool.h>
> +__attribute__((target("sse4.1")))
> +bool f128(char *a)
> +{
> + char t[] = "012345678901234";
> + return __builtin_memcmp(a, &t[0], sizeof(t)) == 0;
> +}
> +
> +__attribute__((target("avx")))
> +bool f256(char *a)
> +{
> + char t[] = "0123456789012345678901234567890";
> + return __builtin_memcmp(a, &t[0], sizeof(t)) == 0;
> +}
> --
> 2.18.1
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] Expand __builtin_memcmp_eq with ptest for OI/TImode.
2022-05-05 7:49 ` Richard Biener
@ 2022-05-05 8:08 ` Uros Bizjak
2022-05-05 8:21 ` Uros Bizjak
2022-05-05 8:22 ` Hongtao Liu
0 siblings, 2 replies; 14+ messages in thread
From: Uros Bizjak @ 2022-05-05 8:08 UTC (permalink / raw)
To: Richard Biener, Roger Sayle; +Cc: liuhongt, GCC Patches
On Thu, May 5, 2022 at 9:50 AM Richard Biener via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> On Thu, May 5, 2022 at 9:37 AM liuhongt via Gcc-patches
> <gcc-patches@gcc.gnu.org> wrote:
> >
> > Enable optimization for TImode only under 32-bit target, for 64-bit
> > target there could be extra ineteger <-> sse move regarding psABI,
> > not efficient.
> >
> > Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}
> > Ok for trunk?
>
> I wonder if this is better done in STV where we could assess this extra cost?
Yes, this should be handled via STV, Roger Sayle (CC'd) has proposed a
patch that does just that.
Uros.
> > gcc/ChangeLog:
> >
> > PR target/104610
> > * config/i386/i386-expand.cc (ix86_expand_branch): Use ptest
> > for TI/QImode when code is EQ or NE.
> > * config/i386/i386.md (SDWIM1248): New iterator.
> > (cbranch<mode>4): Split TImode into a separate expander.
> > (cbranchti4): New expander.
> > * config/i386/predicates.md (timode_comparison_operator): New
> > predicate.
> > * config/i386/sse.md (cbranch<mode>4): Extend to OImode.
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.target/i386/pr104610.c: New test.
> > ---
> > gcc/config/i386/i386-expand.cc | 13 +++++++++++-
> > gcc/config/i386/i386.md | 27 ++++++++++++++++++++++--
> > gcc/config/i386/predicates.md | 6 ++++++
> > gcc/config/i386/sse.md | 10 +++++++--
> > gcc/testsuite/gcc.target/i386/pr104610.c | 23 ++++++++++++++++++++
> > 5 files changed, 74 insertions(+), 5 deletions(-)
> > create mode 100644 gcc/testsuite/gcc.target/i386/pr104610.c
> >
> > diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
> > index bc806ffa283..a2012a158ae 100644
> > --- a/gcc/config/i386/i386-expand.cc
> > +++ b/gcc/config/i386/i386-expand.cc
> > @@ -2264,13 +2264,24 @@ ix86_expand_branch (enum rtx_code code, rtx op0, rtx op1, rtx label)
> > {
> > machine_mode mode = GET_MODE (op0);
> > rtx tmp;
> > + machine_mode p_mode = GET_MODE_SIZE (mode) == 32 ? V4DImode : V2DImode;
> > + /* Using ptest for TImode only for 32-bit target since it's splitted into
> > + 4 comparisons. For 64-bit target there could be extra ineteger <-> sse
> > + move regarding psABI, not efficient. */
> > + if ((code == EQ || code == NE)
> > + && ((mode == OImode && TARGET_AVX)
> > + || (mode == TImode && !TARGET_64BIT && TARGET_SSE4_1)))
> > + {
> > + op0 = lowpart_subreg (p_mode, force_reg (mode, op0), mode);
> > + op1 = lowpart_subreg (p_mode, force_reg (mode, op1), mode);
> > + mode = p_mode;
> > + }
> >
> > /* Handle special case - vector comparsion with boolean result, transform
> > it using ptest instruction. */
> > if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
> > {
> > rtx flag = gen_rtx_REG (CCZmode, FLAGS_REG);
> > - machine_mode p_mode = GET_MODE_SIZE (mode) == 32 ? V4DImode : V2DImode;
> >
> > gcc_assert (code == EQ || code == NE);
> > /* Generate XOR since we can't check that one operand is zero vector. */
> > diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
> > index b321cda1f22..f91325015c9 100644
> > --- a/gcc/config/i386/i386.md
> > +++ b/gcc/config/i386/i386.md
> > @@ -1069,6 +1069,10 @@ (define_mode_iterator SDWIM [(QI "TARGET_QIMODE_MATH")
> > (HI "TARGET_HIMODE_MATH")
> > SI DI (TI "TARGET_64BIT")])
> >
> > +(define_mode_iterator SDWIM1248 [(QI "TARGET_QIMODE_MATH")
> > + (HI "TARGET_HIMODE_MATH")
> > + SI DI])
> > +
> > ;; Math-dependant single word integer modes.
> > (define_mode_iterator SWIM [(QI "TARGET_QIMODE_MATH")
> > (HI "TARGET_HIMODE_MATH")
> > @@ -1322,8 +1326,8 @@ (define_mode_iterator PTR
> >
> > (define_expand "cbranch<mode>4"
> > [(set (reg:CC FLAGS_REG)
> > - (compare:CC (match_operand:SDWIM 1 "nonimmediate_operand")
> > - (match_operand:SDWIM 2 "<general_operand>")))
> > + (compare:CC (match_operand:SDWIM1248 1 "nonimmediate_operand")
> > + (match_operand:SDWIM1248 2 "<general_operand>")))
> > (set (pc) (if_then_else
> > (match_operator 0 "ordered_comparison_operator"
> > [(reg:CC FLAGS_REG) (const_int 0)])
> > @@ -1338,6 +1342,25 @@ (define_expand "cbranch<mode>4"
> > DONE;
> > })
> >
> > +(define_expand "cbranchti4"
> > + [(set (reg:CC FLAGS_REG)
> > + (compare:CC (match_operand:TI 1 "nonimmediate_operand")
> > + (match_operand:TI 2 "x86_64_general_operand")))
> > + (set (pc) (if_then_else
> > + (match_operator 0 "timode_comparison_operator"
> > + [(reg:CC FLAGS_REG) (const_int 0)])
> > + (label_ref (match_operand 3))
> > + (pc)))]
> > + "TARGET_64BIT || TARGET_SSE4_1"
> > +{
> > + if (MEM_P (operands[1]) && MEM_P (operands[2]))
> > + operands[1] = force_reg (TImode, operands[1]);
> > +
> > + ix86_expand_branch (GET_CODE (operands[0]),
> > + operands[1], operands[2], operands[3]);
> > + DONE;
> > +})
> > +
> > (define_expand "cstore<mode>4"
> > [(set (reg:CC FLAGS_REG)
> > (compare:CC (match_operand:SWIM 2 "nonimmediate_operand")
> > diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
> > index a8cc17a054d..fb3be3a262f 100644
> > --- a/gcc/config/i386/predicates.md
> > +++ b/gcc/config/i386/predicates.md
> > @@ -1414,6 +1414,12 @@ (define_predicate "ix86_comparison_uns_operator"
> > (define_predicate "bt_comparison_operator"
> > (match_code "ne,eq"))
> >
> > +(define_predicate "timode_comparison_operator"
> > + (ior (and (match_test "TARGET_SSE4_1")
> > + (match_operand 0 "bt_comparison_operator"))
> > + (and (match_test "TARGET_64BIT")
> > + (match_operand 0 "ordered_comparison_operator"))))
> > +
> > (define_predicate "shr_comparison_operator"
> > (match_code "gtu,leu"))
> >
> > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> > index 7b791def542..0d194cee769 100644
> > --- a/gcc/config/i386/sse.md
> > +++ b/gcc/config/i386/sse.md
> > @@ -26034,10 +26034,14 @@ (define_expand "maskstore<mode><avx512fmaskmodelower>"
> > (match_operand:<avx512fmaskmode> 2 "register_operand")))]
> > "TARGET_AVX512BW")
> >
> > +(define_mode_iterator VI48_OI_AVX
> > + [(V8SI "TARGET_AVX") (V4DI "TARGET_AVX") (OI "TARGET_AVX")
> > + V4SI V2DI])
> > +
> > (define_expand "cbranch<mode>4"
> > [(set (reg:CC FLAGS_REG)
> > - (compare:CC (match_operand:VI48_AVX 1 "register_operand")
> > - (match_operand:VI48_AVX 2 "nonimmediate_operand")))
> > + (compare:CC (match_operand:VI48_OI_AVX 1 "register_operand")
> > + (match_operand:VI48_OI_AVX 2 "nonimmediate_operand")))
> > (set (pc) (if_then_else
> > (match_operator 0 "bt_comparison_operator"
> > [(reg:CC FLAGS_REG) (const_int 0)])
> > @@ -26045,6 +26049,8 @@ (define_expand "cbranch<mode>4"
> > (pc)))]
> > "TARGET_SSE4_1"
> > {
> > + if (!vector_operand (operands[2], <MODE>mode))
> > + operands[2] = force_reg (<MODE>mode, operands[2]);
> > ix86_expand_branch (GET_CODE (operands[0]),
> > operands[1], operands[2], operands[3]);
> > DONE;
> > diff --git a/gcc/testsuite/gcc.target/i386/pr104610.c b/gcc/testsuite/gcc.target/i386/pr104610.c
> > new file mode 100644
> > index 00000000000..68f548594fd
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/i386/pr104610.c
> > @@ -0,0 +1,23 @@
> > +/* { dg-do compile } */
> > +/* { dg-options "-O2 -mmove-max=256 -mstore-max=256" } */
> > +/* { dg-final { scan-assembler-times {(?n)ptest.*xmm} 1 { target ia32 } } } */
> > +/* { dg-final { scan-assembler-times {(?n)vptest.*ymm} 1 } } */
> > +/* { dg-final { scan-assembler-times {sete} 2 } } */
> > +/* { dg-final { scan-assembler-not {(?n)je.*L[0-9]} } } */
> > +/* { dg-final { scan-assembler-not {(?n)jne.*L[0-9]} } } */
> > +
> > +
> > +#include<stdbool.h>
> > +__attribute__((target("sse4.1")))
> > +bool f128(char *a)
> > +{
> > + char t[] = "012345678901234";
> > + return __builtin_memcmp(a, &t[0], sizeof(t)) == 0;
> > +}
> > +
> > +__attribute__((target("avx")))
> > +bool f256(char *a)
> > +{
> > + char t[] = "0123456789012345678901234567890";
> > + return __builtin_memcmp(a, &t[0], sizeof(t)) == 0;
> > +}
> > --
> > 2.18.1
> >
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] Expand __builtin_memcmp_eq with ptest for OI/TImode.
2022-05-05 8:08 ` Uros Bizjak
@ 2022-05-05 8:21 ` Uros Bizjak
2022-05-05 8:22 ` Hongtao Liu
1 sibling, 0 replies; 14+ messages in thread
From: Uros Bizjak @ 2022-05-05 8:21 UTC (permalink / raw)
To: Richard Biener, Roger Sayle; +Cc: liuhongt, GCC Patches
On Thu, May 5, 2022 at 10:08 AM Uros Bizjak <ubizjak@gmail.com> wrote:
>
> On Thu, May 5, 2022 at 9:50 AM Richard Biener via Gcc-patches
> <gcc-patches@gcc.gnu.org> wrote:
> >
> > On Thu, May 5, 2022 at 9:37 AM liuhongt via Gcc-patches
> > <gcc-patches@gcc.gnu.org> wrote:
> > >
> > > Enable optimization for TImode only under 32-bit target, for 64-bit
> > > target there could be extra ineteger <-> sse move regarding psABI,
> > > not efficient.
> > >
> > > Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}
> > > Ok for trunk?
> >
> > I wonder if this is better done in STV where we could assess this extra cost?
>
> Yes, this should be handled via STV, Roger Sayle (CC'd) has proposed a
> patch that does just that.
https://gcc.gnu.org/pipermail/gcc-patches/2022-April/593174.html
Uros.
>
> > > gcc/ChangeLog:
> > >
> > > PR target/104610
> > > * config/i386/i386-expand.cc (ix86_expand_branch): Use ptest
> > > for TI/QImode when code is EQ or NE.
> > > * config/i386/i386.md (SDWIM1248): New iterator.
> > > (cbranch<mode>4): Split TImode into a separate expander.
> > > (cbranchti4): New expander.
> > > * config/i386/predicates.md (timode_comparison_operator): New
> > > predicate.
> > > * config/i386/sse.md (cbranch<mode>4): Extend to OImode.
> > >
> > > gcc/testsuite/ChangeLog:
> > >
> > > * gcc.target/i386/pr104610.c: New test.
> > > ---
> > > gcc/config/i386/i386-expand.cc | 13 +++++++++++-
> > > gcc/config/i386/i386.md | 27 ++++++++++++++++++++++--
> > > gcc/config/i386/predicates.md | 6 ++++++
> > > gcc/config/i386/sse.md | 10 +++++++--
> > > gcc/testsuite/gcc.target/i386/pr104610.c | 23 ++++++++++++++++++++
> > > 5 files changed, 74 insertions(+), 5 deletions(-)
> > > create mode 100644 gcc/testsuite/gcc.target/i386/pr104610.c
> > >
> > > diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
> > > index bc806ffa283..a2012a158ae 100644
> > > --- a/gcc/config/i386/i386-expand.cc
> > > +++ b/gcc/config/i386/i386-expand.cc
> > > @@ -2264,13 +2264,24 @@ ix86_expand_branch (enum rtx_code code, rtx op0, rtx op1, rtx label)
> > > {
> > > machine_mode mode = GET_MODE (op0);
> > > rtx tmp;
> > > + machine_mode p_mode = GET_MODE_SIZE (mode) == 32 ? V4DImode : V2DImode;
> > > + /* Using ptest for TImode only for 32-bit target since it's splitted into
> > > + 4 comparisons. For 64-bit target there could be extra ineteger <-> sse
> > > + move regarding psABI, not efficient. */
> > > + if ((code == EQ || code == NE)
> > > + && ((mode == OImode && TARGET_AVX)
> > > + || (mode == TImode && !TARGET_64BIT && TARGET_SSE4_1)))
> > > + {
> > > + op0 = lowpart_subreg (p_mode, force_reg (mode, op0), mode);
> > > + op1 = lowpart_subreg (p_mode, force_reg (mode, op1), mode);
> > > + mode = p_mode;
> > > + }
> > >
> > > /* Handle special case - vector comparsion with boolean result, transform
> > > it using ptest instruction. */
> > > if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
> > > {
> > > rtx flag = gen_rtx_REG (CCZmode, FLAGS_REG);
> > > - machine_mode p_mode = GET_MODE_SIZE (mode) == 32 ? V4DImode : V2DImode;
> > >
> > > gcc_assert (code == EQ || code == NE);
> > > /* Generate XOR since we can't check that one operand is zero vector. */
> > > diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
> > > index b321cda1f22..f91325015c9 100644
> > > --- a/gcc/config/i386/i386.md
> > > +++ b/gcc/config/i386/i386.md
> > > @@ -1069,6 +1069,10 @@ (define_mode_iterator SDWIM [(QI "TARGET_QIMODE_MATH")
> > > (HI "TARGET_HIMODE_MATH")
> > > SI DI (TI "TARGET_64BIT")])
> > >
> > > +(define_mode_iterator SDWIM1248 [(QI "TARGET_QIMODE_MATH")
> > > + (HI "TARGET_HIMODE_MATH")
> > > + SI DI])
> > > +
> > > ;; Math-dependant single word integer modes.
> > > (define_mode_iterator SWIM [(QI "TARGET_QIMODE_MATH")
> > > (HI "TARGET_HIMODE_MATH")
> > > @@ -1322,8 +1326,8 @@ (define_mode_iterator PTR
> > >
> > > (define_expand "cbranch<mode>4"
> > > [(set (reg:CC FLAGS_REG)
> > > - (compare:CC (match_operand:SDWIM 1 "nonimmediate_operand")
> > > - (match_operand:SDWIM 2 "<general_operand>")))
> > > + (compare:CC (match_operand:SDWIM1248 1 "nonimmediate_operand")
> > > + (match_operand:SDWIM1248 2 "<general_operand>")))
> > > (set (pc) (if_then_else
> > > (match_operator 0 "ordered_comparison_operator"
> > > [(reg:CC FLAGS_REG) (const_int 0)])
> > > @@ -1338,6 +1342,25 @@ (define_expand "cbranch<mode>4"
> > > DONE;
> > > })
> > >
> > > +(define_expand "cbranchti4"
> > > + [(set (reg:CC FLAGS_REG)
> > > + (compare:CC (match_operand:TI 1 "nonimmediate_operand")
> > > + (match_operand:TI 2 "x86_64_general_operand")))
> > > + (set (pc) (if_then_else
> > > + (match_operator 0 "timode_comparison_operator"
> > > + [(reg:CC FLAGS_REG) (const_int 0)])
> > > + (label_ref (match_operand 3))
> > > + (pc)))]
> > > + "TARGET_64BIT || TARGET_SSE4_1"
> > > +{
> > > + if (MEM_P (operands[1]) && MEM_P (operands[2]))
> > > + operands[1] = force_reg (TImode, operands[1]);
> > > +
> > > + ix86_expand_branch (GET_CODE (operands[0]),
> > > + operands[1], operands[2], operands[3]);
> > > + DONE;
> > > +})
> > > +
> > > (define_expand "cstore<mode>4"
> > > [(set (reg:CC FLAGS_REG)
> > > (compare:CC (match_operand:SWIM 2 "nonimmediate_operand")
> > > diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
> > > index a8cc17a054d..fb3be3a262f 100644
> > > --- a/gcc/config/i386/predicates.md
> > > +++ b/gcc/config/i386/predicates.md
> > > @@ -1414,6 +1414,12 @@ (define_predicate "ix86_comparison_uns_operator"
> > > (define_predicate "bt_comparison_operator"
> > > (match_code "ne,eq"))
> > >
> > > +(define_predicate "timode_comparison_operator"
> > > + (ior (and (match_test "TARGET_SSE4_1")
> > > + (match_operand 0 "bt_comparison_operator"))
> > > + (and (match_test "TARGET_64BIT")
> > > + (match_operand 0 "ordered_comparison_operator"))))
> > > +
> > > (define_predicate "shr_comparison_operator"
> > > (match_code "gtu,leu"))
> > >
> > > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> > > index 7b791def542..0d194cee769 100644
> > > --- a/gcc/config/i386/sse.md
> > > +++ b/gcc/config/i386/sse.md
> > > @@ -26034,10 +26034,14 @@ (define_expand "maskstore<mode><avx512fmaskmodelower>"
> > > (match_operand:<avx512fmaskmode> 2 "register_operand")))]
> > > "TARGET_AVX512BW")
> > >
> > > +(define_mode_iterator VI48_OI_AVX
> > > + [(V8SI "TARGET_AVX") (V4DI "TARGET_AVX") (OI "TARGET_AVX")
> > > + V4SI V2DI])
> > > +
> > > (define_expand "cbranch<mode>4"
> > > [(set (reg:CC FLAGS_REG)
> > > - (compare:CC (match_operand:VI48_AVX 1 "register_operand")
> > > - (match_operand:VI48_AVX 2 "nonimmediate_operand")))
> > > + (compare:CC (match_operand:VI48_OI_AVX 1 "register_operand")
> > > + (match_operand:VI48_OI_AVX 2 "nonimmediate_operand")))
> > > (set (pc) (if_then_else
> > > (match_operator 0 "bt_comparison_operator"
> > > [(reg:CC FLAGS_REG) (const_int 0)])
> > > @@ -26045,6 +26049,8 @@ (define_expand "cbranch<mode>4"
> > > (pc)))]
> > > "TARGET_SSE4_1"
> > > {
> > > + if (!vector_operand (operands[2], <MODE>mode))
> > > + operands[2] = force_reg (<MODE>mode, operands[2]);
> > > ix86_expand_branch (GET_CODE (operands[0]),
> > > operands[1], operands[2], operands[3]);
> > > DONE;
> > > diff --git a/gcc/testsuite/gcc.target/i386/pr104610.c b/gcc/testsuite/gcc.target/i386/pr104610.c
> > > new file mode 100644
> > > index 00000000000..68f548594fd
> > > --- /dev/null
> > > +++ b/gcc/testsuite/gcc.target/i386/pr104610.c
> > > @@ -0,0 +1,23 @@
> > > +/* { dg-do compile } */
> > > +/* { dg-options "-O2 -mmove-max=256 -mstore-max=256" } */
> > > +/* { dg-final { scan-assembler-times {(?n)ptest.*xmm} 1 { target ia32 } } } */
> > > +/* { dg-final { scan-assembler-times {(?n)vptest.*ymm} 1 } } */
> > > +/* { dg-final { scan-assembler-times {sete} 2 } } */
> > > +/* { dg-final { scan-assembler-not {(?n)je.*L[0-9]} } } */
> > > +/* { dg-final { scan-assembler-not {(?n)jne.*L[0-9]} } } */
> > > +
> > > +
> > > +#include<stdbool.h>
> > > +__attribute__((target("sse4.1")))
> > > +bool f128(char *a)
> > > +{
> > > + char t[] = "012345678901234";
> > > + return __builtin_memcmp(a, &t[0], sizeof(t)) == 0;
> > > +}
> > > +
> > > +__attribute__((target("avx")))
> > > +bool f256(char *a)
> > > +{
> > > + char t[] = "0123456789012345678901234567890";
> > > + return __builtin_memcmp(a, &t[0], sizeof(t)) == 0;
> > > +}
> > > --
> > > 2.18.1
> > >
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] Expand __builtin_memcmp_eq with ptest for OI/TImode.
2022-05-05 8:08 ` Uros Bizjak
2022-05-05 8:21 ` Uros Bizjak
@ 2022-05-05 8:22 ` Hongtao Liu
2022-05-05 8:30 ` Uros Bizjak
1 sibling, 1 reply; 14+ messages in thread
From: Hongtao Liu @ 2022-05-05 8:22 UTC (permalink / raw)
To: Uros Bizjak; +Cc: Richard Biener, Roger Sayle, liuhongt, GCC Patches
On Thu, May 5, 2022 at 4:09 PM Uros Bizjak via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> On Thu, May 5, 2022 at 9:50 AM Richard Biener via Gcc-patches
> <gcc-patches@gcc.gnu.org> wrote:
> >
> > On Thu, May 5, 2022 at 9:37 AM liuhongt via Gcc-patches
> > <gcc-patches@gcc.gnu.org> wrote:
> > >
> > > Enable optimization for TImode only under 32-bit target, for 64-bit
> > > target there could be extra ineteger <-> sse move regarding psABI,
> > > not efficient.
> > >
> > > Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}
> > > Ok for trunk?
> >
> > I wonder if this is better done in STV where we could assess this extra cost?
>
> Yes, this should be handled via STV, Roger Sayle (CC'd) has proposed a
> patch that does just that.
>
My patch also handles OImode, I think that part could be a separate patch.
>
> Uros.
>
> > > gcc/ChangeLog:
> > >
> > > PR target/104610
> > > * config/i386/i386-expand.cc (ix86_expand_branch): Use ptest
> > > for TI/QImode when code is EQ or NE.
> > > * config/i386/i386.md (SDWIM1248): New iterator.
> > > (cbranch<mode>4): Split TImode into a separate expander.
> > > (cbranchti4): New expander.
> > > * config/i386/predicates.md (timode_comparison_operator): New
> > > predicate.
> > > * config/i386/sse.md (cbranch<mode>4): Extend to OImode.
> > >
> > > gcc/testsuite/ChangeLog:
> > >
> > > * gcc.target/i386/pr104610.c: New test.
> > > ---
> > > gcc/config/i386/i386-expand.cc | 13 +++++++++++-
> > > gcc/config/i386/i386.md | 27 ++++++++++++++++++++++--
> > > gcc/config/i386/predicates.md | 6 ++++++
> > > gcc/config/i386/sse.md | 10 +++++++--
> > > gcc/testsuite/gcc.target/i386/pr104610.c | 23 ++++++++++++++++++++
> > > 5 files changed, 74 insertions(+), 5 deletions(-)
> > > create mode 100644 gcc/testsuite/gcc.target/i386/pr104610.c
> > >
> > > diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
> > > index bc806ffa283..a2012a158ae 100644
> > > --- a/gcc/config/i386/i386-expand.cc
> > > +++ b/gcc/config/i386/i386-expand.cc
> > > @@ -2264,13 +2264,24 @@ ix86_expand_branch (enum rtx_code code, rtx op0, rtx op1, rtx label)
> > > {
> > > machine_mode mode = GET_MODE (op0);
> > > rtx tmp;
> > > + machine_mode p_mode = GET_MODE_SIZE (mode) == 32 ? V4DImode : V2DImode;
> > > + /* Using ptest for TImode only for 32-bit target since it's splitted into
> > > + 4 comparisons. For 64-bit target there could be extra ineteger <-> sse
> > > + move regarding psABI, not efficient. */
> > > + if ((code == EQ || code == NE)
> > > + && ((mode == OImode && TARGET_AVX)
> > > + || (mode == TImode && !TARGET_64BIT && TARGET_SSE4_1)))
> > > + {
> > > + op0 = lowpart_subreg (p_mode, force_reg (mode, op0), mode);
> > > + op1 = lowpart_subreg (p_mode, force_reg (mode, op1), mode);
> > > + mode = p_mode;
> > > + }
> > >
> > > /* Handle special case - vector comparsion with boolean result, transform
> > > it using ptest instruction. */
> > > if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
> > > {
> > > rtx flag = gen_rtx_REG (CCZmode, FLAGS_REG);
> > > - machine_mode p_mode = GET_MODE_SIZE (mode) == 32 ? V4DImode : V2DImode;
> > >
> > > gcc_assert (code == EQ || code == NE);
> > > /* Generate XOR since we can't check that one operand is zero vector. */
> > > diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
> > > index b321cda1f22..f91325015c9 100644
> > > --- a/gcc/config/i386/i386.md
> > > +++ b/gcc/config/i386/i386.md
> > > @@ -1069,6 +1069,10 @@ (define_mode_iterator SDWIM [(QI "TARGET_QIMODE_MATH")
> > > (HI "TARGET_HIMODE_MATH")
> > > SI DI (TI "TARGET_64BIT")])
> > >
> > > +(define_mode_iterator SDWIM1248 [(QI "TARGET_QIMODE_MATH")
> > > + (HI "TARGET_HIMODE_MATH")
> > > + SI DI])
> > > +
> > > ;; Math-dependant single word integer modes.
> > > (define_mode_iterator SWIM [(QI "TARGET_QIMODE_MATH")
> > > (HI "TARGET_HIMODE_MATH")
> > > @@ -1322,8 +1326,8 @@ (define_mode_iterator PTR
> > >
> > > (define_expand "cbranch<mode>4"
> > > [(set (reg:CC FLAGS_REG)
> > > - (compare:CC (match_operand:SDWIM 1 "nonimmediate_operand")
> > > - (match_operand:SDWIM 2 "<general_operand>")))
> > > + (compare:CC (match_operand:SDWIM1248 1 "nonimmediate_operand")
> > > + (match_operand:SDWIM1248 2 "<general_operand>")))
> > > (set (pc) (if_then_else
> > > (match_operator 0 "ordered_comparison_operator"
> > > [(reg:CC FLAGS_REG) (const_int 0)])
> > > @@ -1338,6 +1342,25 @@ (define_expand "cbranch<mode>4"
> > > DONE;
> > > })
> > >
> > > +(define_expand "cbranchti4"
> > > + [(set (reg:CC FLAGS_REG)
> > > + (compare:CC (match_operand:TI 1 "nonimmediate_operand")
> > > + (match_operand:TI 2 "x86_64_general_operand")))
> > > + (set (pc) (if_then_else
> > > + (match_operator 0 "timode_comparison_operator"
> > > + [(reg:CC FLAGS_REG) (const_int 0)])
> > > + (label_ref (match_operand 3))
> > > + (pc)))]
> > > + "TARGET_64BIT || TARGET_SSE4_1"
> > > +{
> > > + if (MEM_P (operands[1]) && MEM_P (operands[2]))
> > > + operands[1] = force_reg (TImode, operands[1]);
> > > +
> > > + ix86_expand_branch (GET_CODE (operands[0]),
> > > + operands[1], operands[2], operands[3]);
> > > + DONE;
> > > +})
> > > +
> > > (define_expand "cstore<mode>4"
> > > [(set (reg:CC FLAGS_REG)
> > > (compare:CC (match_operand:SWIM 2 "nonimmediate_operand")
> > > diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
> > > index a8cc17a054d..fb3be3a262f 100644
> > > --- a/gcc/config/i386/predicates.md
> > > +++ b/gcc/config/i386/predicates.md
> > > @@ -1414,6 +1414,12 @@ (define_predicate "ix86_comparison_uns_operator"
> > > (define_predicate "bt_comparison_operator"
> > > (match_code "ne,eq"))
> > >
> > > +(define_predicate "timode_comparison_operator"
> > > + (ior (and (match_test "TARGET_SSE4_1")
> > > + (match_operand 0 "bt_comparison_operator"))
> > > + (and (match_test "TARGET_64BIT")
> > > + (match_operand 0 "ordered_comparison_operator"))))
> > > +
> > > (define_predicate "shr_comparison_operator"
> > > (match_code "gtu,leu"))
> > >
> > > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> > > index 7b791def542..0d194cee769 100644
> > > --- a/gcc/config/i386/sse.md
> > > +++ b/gcc/config/i386/sse.md
> > > @@ -26034,10 +26034,14 @@ (define_expand "maskstore<mode><avx512fmaskmodelower>"
> > > (match_operand:<avx512fmaskmode> 2 "register_operand")))]
> > > "TARGET_AVX512BW")
> > >
> > > +(define_mode_iterator VI48_OI_AVX
> > > + [(V8SI "TARGET_AVX") (V4DI "TARGET_AVX") (OI "TARGET_AVX")
> > > + V4SI V2DI])
> > > +
> > > (define_expand "cbranch<mode>4"
> > > [(set (reg:CC FLAGS_REG)
> > > - (compare:CC (match_operand:VI48_AVX 1 "register_operand")
> > > - (match_operand:VI48_AVX 2 "nonimmediate_operand")))
> > > + (compare:CC (match_operand:VI48_OI_AVX 1 "register_operand")
> > > + (match_operand:VI48_OI_AVX 2 "nonimmediate_operand")))
> > > (set (pc) (if_then_else
> > > (match_operator 0 "bt_comparison_operator"
> > > [(reg:CC FLAGS_REG) (const_int 0)])
> > > @@ -26045,6 +26049,8 @@ (define_expand "cbranch<mode>4"
> > > (pc)))]
> > > "TARGET_SSE4_1"
> > > {
> > > + if (!vector_operand (operands[2], <MODE>mode))
> > > + operands[2] = force_reg (<MODE>mode, operands[2]);
> > > ix86_expand_branch (GET_CODE (operands[0]),
> > > operands[1], operands[2], operands[3]);
> > > DONE;
> > > diff --git a/gcc/testsuite/gcc.target/i386/pr104610.c b/gcc/testsuite/gcc.target/i386/pr104610.c
> > > new file mode 100644
> > > index 00000000000..68f548594fd
> > > --- /dev/null
> > > +++ b/gcc/testsuite/gcc.target/i386/pr104610.c
> > > @@ -0,0 +1,23 @@
> > > +/* { dg-do compile } */
> > > +/* { dg-options "-O2 -mmove-max=256 -mstore-max=256" } */
> > > +/* { dg-final { scan-assembler-times {(?n)ptest.*xmm} 1 { target ia32 } } } */
> > > +/* { dg-final { scan-assembler-times {(?n)vptest.*ymm} 1 } } */
> > > +/* { dg-final { scan-assembler-times {sete} 2 } } */
> > > +/* { dg-final { scan-assembler-not {(?n)je.*L[0-9]} } } */
> > > +/* { dg-final { scan-assembler-not {(?n)jne.*L[0-9]} } } */
> > > +
> > > +
> > > +#include<stdbool.h>
> > > +__attribute__((target("sse4.1")))
> > > +bool f128(char *a)
> > > +{
> > > + char t[] = "012345678901234";
> > > + return __builtin_memcmp(a, &t[0], sizeof(t)) == 0;
> > > +}
> > > +
> > > +__attribute__((target("avx")))
> > > +bool f256(char *a)
> > > +{
> > > + char t[] = "0123456789012345678901234567890";
> > > + return __builtin_memcmp(a, &t[0], sizeof(t)) == 0;
> > > +}
> > > --
> > > 2.18.1
> > >
--
BR,
Hongtao
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] Expand __builtin_memcmp_eq with ptest for OI/TImode.
2022-05-05 8:22 ` Hongtao Liu
@ 2022-05-05 8:30 ` Uros Bizjak
2022-05-07 5:05 ` [PATCH] Expand __builtin_memcmp_eq with ptest for OImode liuhongt
0 siblings, 1 reply; 14+ messages in thread
From: Uros Bizjak @ 2022-05-05 8:30 UTC (permalink / raw)
To: Hongtao Liu; +Cc: Richard Biener, Roger Sayle, liuhongt, GCC Patches
On Thu, May 5, 2022 at 10:23 AM Hongtao Liu <crazylht@gmail.com> wrote:
>
> On Thu, May 5, 2022 at 4:09 PM Uros Bizjak via Gcc-patches
> <gcc-patches@gcc.gnu.org> wrote:
> >
> > On Thu, May 5, 2022 at 9:50 AM Richard Biener via Gcc-patches
> > <gcc-patches@gcc.gnu.org> wrote:
> > >
> > > On Thu, May 5, 2022 at 9:37 AM liuhongt via Gcc-patches
> > > <gcc-patches@gcc.gnu.org> wrote:
> > > >
> > > > Enable optimization for TImode only under 32-bit target, for 64-bit
> > > > target there could be extra ineteger <-> sse move regarding psABI,
> > > > not efficient.
> > > >
> > > > Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}
> > > > Ok for trunk?
> > >
> > > I wonder if this is better done in STV where we could assess this extra cost?
> >
> > Yes, this should be handled via STV, Roger Sayle (CC'd) has proposed a
> > patch that does just that.
> >
> My patch also handles OImode, I think that part could be a separate patch.
Yes, OImode (and TImode on x86_32) can't be implemented using integer registers.
Uros,
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH] Expand __builtin_memcmp_eq with ptest for OImode.
2022-05-05 8:30 ` Uros Bizjak
@ 2022-05-07 5:05 ` liuhongt
2022-05-09 0:57 ` Hongtao Liu
` (2 more replies)
0 siblings, 3 replies; 14+ messages in thread
From: liuhongt @ 2022-05-07 5:05 UTC (permalink / raw)
To: gcc-patches
This is adjusted patch only for OImode.
Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
Ok for trunk?
gcc/ChangeLog:
PR target/104610
* config/i386/i386-expand.cc (ix86_expand_branch): Use ptest
for QImode when code is EQ or NE.
* config/i386/sse.md (cbranch<mode>4): Extend to OImode.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr104610.c: New test.
---
gcc/config/i386/i386-expand.cc | 10 +++++++++-
gcc/config/i386/sse.md | 8 ++++++--
gcc/testsuite/gcc.target/i386/pr104610.c | 15 +++++++++++++++
3 files changed, 30 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/i386/pr104610.c
diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index bc806ffa283..c2f8776102c 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -2267,11 +2267,19 @@ ix86_expand_branch (enum rtx_code code, rtx op0, rtx op1, rtx label)
/* Handle special case - vector comparsion with boolean result, transform
it using ptest instruction. */
- if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
+ if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
+ || (mode == OImode && (code == EQ || code == NE)))
{
rtx flag = gen_rtx_REG (CCZmode, FLAGS_REG);
machine_mode p_mode = GET_MODE_SIZE (mode) == 32 ? V4DImode : V2DImode;
+ if (mode == OImode)
+ {
+ op0 = lowpart_subreg (p_mode, force_reg (mode, op0), mode);
+ op1 = lowpart_subreg (p_mode, force_reg (mode, op1), mode);
+ mode = p_mode;
+ }
+
gcc_assert (code == EQ || code == NE);
/* Generate XOR since we can't check that one operand is zero vector. */
tmp = gen_reg_rtx (mode);
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 7b791def542..9514b8e0234 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -26034,10 +26034,14 @@ (define_expand "maskstore<mode><avx512fmaskmodelower>"
(match_operand:<avx512fmaskmode> 2 "register_operand")))]
"TARGET_AVX512BW")
+(define_mode_iterator VI48_OI_AVX
+ [(V8SI "TARGET_AVX") (V4DI "TARGET_AVX") (OI "TARGET_AVX")
+ V4SI V2DI])
+
(define_expand "cbranch<mode>4"
[(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand:VI48_AVX 1 "register_operand")
- (match_operand:VI48_AVX 2 "nonimmediate_operand")))
+ (compare:CC (match_operand:VI48_OI_AVX 1 "register_operand")
+ (match_operand:VI48_OI_AVX 2 "nonimmediate_operand")))
(set (pc) (if_then_else
(match_operator 0 "bt_comparison_operator"
[(reg:CC FLAGS_REG) (const_int 0)])
diff --git a/gcc/testsuite/gcc.target/i386/pr104610.c b/gcc/testsuite/gcc.target/i386/pr104610.c
new file mode 100644
index 00000000000..00866238bd7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr104610.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mmove-max=256 -mstore-max=256" } */
+/* { dg-final { scan-assembler-times {(?n)vptest.*ymm} 1 } } */
+/* { dg-final { scan-assembler-times {sete} 1 } } */
+/* { dg-final { scan-assembler-not {(?n)je.*L[0-9]} } } */
+/* { dg-final { scan-assembler-not {(?n)jne.*L[0-9]} } } */
+
+
+#include<stdbool.h>
+__attribute__((target("avx")))
+bool f256(char *a)
+{
+ char t[] = "0123456789012345678901234567890";
+ return __builtin_memcmp(a, &t[0], sizeof(t)) == 0;
+}
--
2.18.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] Expand __builtin_memcmp_eq with ptest for OImode.
2022-05-07 5:05 ` [PATCH] Expand __builtin_memcmp_eq with ptest for OImode liuhongt
@ 2022-05-09 0:57 ` Hongtao Liu
2022-05-16 1:47 ` Hongtao Liu
2022-05-16 9:10 ` Uros Bizjak
2 siblings, 0 replies; 14+ messages in thread
From: Hongtao Liu @ 2022-05-09 0:57 UTC (permalink / raw)
To: Uros Bizjak; +Cc: GCC Patches
On Sat, May 7, 2022 at 1:05 PM liuhongt via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> This is adjusted patch only for OImode.
>
> Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
> Ok for trunk?
>
> gcc/ChangeLog:
>
> PR target/104610
> * config/i386/i386-expand.cc (ix86_expand_branch): Use ptest
> for QImode when code is EQ or NE.
> * config/i386/sse.md (cbranch<mode>4): Extend to OImode.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/i386/pr104610.c: New test.
> ---
> gcc/config/i386/i386-expand.cc | 10 +++++++++-
> gcc/config/i386/sse.md | 8 ++++++--
> gcc/testsuite/gcc.target/i386/pr104610.c | 15 +++++++++++++++
> 3 files changed, 30 insertions(+), 3 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/i386/pr104610.c
>
> diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
> index bc806ffa283..c2f8776102c 100644
> --- a/gcc/config/i386/i386-expand.cc
> +++ b/gcc/config/i386/i386-expand.cc
> @@ -2267,11 +2267,19 @@ ix86_expand_branch (enum rtx_code code, rtx op0, rtx op1, rtx label)
>
> /* Handle special case - vector comparsion with boolean result, transform
> it using ptest instruction. */
> - if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
> + if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
> + || (mode == OImode && (code == EQ || code == NE)))
> {
> rtx flag = gen_rtx_REG (CCZmode, FLAGS_REG);
> machine_mode p_mode = GET_MODE_SIZE (mode) == 32 ? V4DImode : V2DImode;
>
> + if (mode == OImode)
> + {
> + op0 = lowpart_subreg (p_mode, force_reg (mode, op0), mode);
> + op1 = lowpart_subreg (p_mode, force_reg (mode, op1), mode);
> + mode = p_mode;
> + }
> +
> gcc_assert (code == EQ || code == NE);
> /* Generate XOR since we can't check that one operand is zero vector. */
> tmp = gen_reg_rtx (mode);
> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> index 7b791def542..9514b8e0234 100644
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -26034,10 +26034,14 @@ (define_expand "maskstore<mode><avx512fmaskmodelower>"
> (match_operand:<avx512fmaskmode> 2 "register_operand")))]
> "TARGET_AVX512BW")
>
> +(define_mode_iterator VI48_OI_AVX
> + [(V8SI "TARGET_AVX") (V4DI "TARGET_AVX") (OI "TARGET_AVX")
> + V4SI V2DI])
> +
> (define_expand "cbranch<mode>4"
> [(set (reg:CC FLAGS_REG)
> - (compare:CC (match_operand:VI48_AVX 1 "register_operand")
> - (match_operand:VI48_AVX 2 "nonimmediate_operand")))
> + (compare:CC (match_operand:VI48_OI_AVX 1 "register_operand")
> + (match_operand:VI48_OI_AVX 2 "nonimmediate_operand")))
> (set (pc) (if_then_else
> (match_operator 0 "bt_comparison_operator"
> [(reg:CC FLAGS_REG) (const_int 0)])
> diff --git a/gcc/testsuite/gcc.target/i386/pr104610.c b/gcc/testsuite/gcc.target/i386/pr104610.c
> new file mode 100644
> index 00000000000..00866238bd7
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr104610.c
> @@ -0,0 +1,15 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -mmove-max=256 -mstore-max=256" } */
> +/* { dg-final { scan-assembler-times {(?n)vptest.*ymm} 1 } } */
> +/* { dg-final { scan-assembler-times {sete} 1 } } */
> +/* { dg-final { scan-assembler-not {(?n)je.*L[0-9]} } } */
> +/* { dg-final { scan-assembler-not {(?n)jne.*L[0-9]} } } */
> +
> +
> +#include<stdbool.h>
> +__attribute__((target("avx")))
> +bool f256(char *a)
> +{
> + char t[] = "0123456789012345678901234567890";
> + return __builtin_memcmp(a, &t[0], sizeof(t)) == 0;
> +}
> --
> 2.18.1
>
--
BR,
Hongtao
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] Expand __builtin_memcmp_eq with ptest for OImode.
2022-05-07 5:05 ` [PATCH] Expand __builtin_memcmp_eq with ptest for OImode liuhongt
2022-05-09 0:57 ` Hongtao Liu
@ 2022-05-16 1:47 ` Hongtao Liu
2022-05-16 9:10 ` Uros Bizjak
2 siblings, 0 replies; 14+ messages in thread
From: Hongtao Liu @ 2022-05-16 1:47 UTC (permalink / raw)
To: Uros Bizjak; +Cc: GCC Patches
ping.
On Sat, May 7, 2022 at 1:05 PM liuhongt via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> This is adjusted patch only for OImode.
>
> Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
> Ok for trunk?
>
> gcc/ChangeLog:
>
> PR target/104610
> * config/i386/i386-expand.cc (ix86_expand_branch): Use ptest
> for QImode when code is EQ or NE.
> * config/i386/sse.md (cbranch<mode>4): Extend to OImode.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/i386/pr104610.c: New test.
> ---
> gcc/config/i386/i386-expand.cc | 10 +++++++++-
> gcc/config/i386/sse.md | 8 ++++++--
> gcc/testsuite/gcc.target/i386/pr104610.c | 15 +++++++++++++++
> 3 files changed, 30 insertions(+), 3 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/i386/pr104610.c
>
> diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
> index bc806ffa283..c2f8776102c 100644
> --- a/gcc/config/i386/i386-expand.cc
> +++ b/gcc/config/i386/i386-expand.cc
> @@ -2267,11 +2267,19 @@ ix86_expand_branch (enum rtx_code code, rtx op0, rtx op1, rtx label)
>
> /* Handle special case - vector comparsion with boolean result, transform
> it using ptest instruction. */
> - if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
> + if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
> + || (mode == OImode && (code == EQ || code == NE)))
> {
> rtx flag = gen_rtx_REG (CCZmode, FLAGS_REG);
> machine_mode p_mode = GET_MODE_SIZE (mode) == 32 ? V4DImode : V2DImode;
>
> + if (mode == OImode)
> + {
> + op0 = lowpart_subreg (p_mode, force_reg (mode, op0), mode);
> + op1 = lowpart_subreg (p_mode, force_reg (mode, op1), mode);
> + mode = p_mode;
> + }
> +
> gcc_assert (code == EQ || code == NE);
> /* Generate XOR since we can't check that one operand is zero vector. */
> tmp = gen_reg_rtx (mode);
> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> index 7b791def542..9514b8e0234 100644
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -26034,10 +26034,14 @@ (define_expand "maskstore<mode><avx512fmaskmodelower>"
> (match_operand:<avx512fmaskmode> 2 "register_operand")))]
> "TARGET_AVX512BW")
>
> +(define_mode_iterator VI48_OI_AVX
> + [(V8SI "TARGET_AVX") (V4DI "TARGET_AVX") (OI "TARGET_AVX")
> + V4SI V2DI])
> +
> (define_expand "cbranch<mode>4"
> [(set (reg:CC FLAGS_REG)
> - (compare:CC (match_operand:VI48_AVX 1 "register_operand")
> - (match_operand:VI48_AVX 2 "nonimmediate_operand")))
> + (compare:CC (match_operand:VI48_OI_AVX 1 "register_operand")
> + (match_operand:VI48_OI_AVX 2 "nonimmediate_operand")))
> (set (pc) (if_then_else
> (match_operator 0 "bt_comparison_operator"
> [(reg:CC FLAGS_REG) (const_int 0)])
> diff --git a/gcc/testsuite/gcc.target/i386/pr104610.c b/gcc/testsuite/gcc.target/i386/pr104610.c
> new file mode 100644
> index 00000000000..00866238bd7
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr104610.c
> @@ -0,0 +1,15 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -mmove-max=256 -mstore-max=256" } */
> +/* { dg-final { scan-assembler-times {(?n)vptest.*ymm} 1 } } */
> +/* { dg-final { scan-assembler-times {sete} 1 } } */
> +/* { dg-final { scan-assembler-not {(?n)je.*L[0-9]} } } */
> +/* { dg-final { scan-assembler-not {(?n)jne.*L[0-9]} } } */
> +
> +
> +#include<stdbool.h>
> +__attribute__((target("avx")))
> +bool f256(char *a)
> +{
> + char t[] = "0123456789012345678901234567890";
> + return __builtin_memcmp(a, &t[0], sizeof(t)) == 0;
> +}
> --
> 2.18.1
>
--
BR,
Hongtao
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] Expand __builtin_memcmp_eq with ptest for OImode.
2022-05-07 5:05 ` [PATCH] Expand __builtin_memcmp_eq with ptest for OImode liuhongt
2022-05-09 0:57 ` Hongtao Liu
2022-05-16 1:47 ` Hongtao Liu
@ 2022-05-16 9:10 ` Uros Bizjak
2022-05-17 1:33 ` Hongtao Liu
2 siblings, 1 reply; 14+ messages in thread
From: Uros Bizjak @ 2022-05-16 9:10 UTC (permalink / raw)
To: liuhongt; +Cc: gcc-patches
On Sat, May 7, 2022 at 7:05 AM liuhongt <hongtao.liu@intel.com> wrote:
>
> This is adjusted patch only for OImode.
>
> Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
> Ok for trunk?
>
> gcc/ChangeLog:
>
> PR target/104610
> * config/i386/i386-expand.cc (ix86_expand_branch): Use ptest
> for QImode when code is EQ or NE.
> * config/i386/sse.md (cbranch<mode>4): Extend to OImode.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/i386/pr104610.c: New test.
> ---
> gcc/config/i386/i386-expand.cc | 10 +++++++++-
> gcc/config/i386/sse.md | 8 ++++++--
> gcc/testsuite/gcc.target/i386/pr104610.c | 15 +++++++++++++++
> 3 files changed, 30 insertions(+), 3 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/i386/pr104610.c
>
> diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
> index bc806ffa283..c2f8776102c 100644
> --- a/gcc/config/i386/i386-expand.cc
> +++ b/gcc/config/i386/i386-expand.cc
> @@ -2267,11 +2267,19 @@ ix86_expand_branch (enum rtx_code code, rtx op0, rtx op1, rtx label)
>
> /* Handle special case - vector comparsion with boolean result, transform
> it using ptest instruction. */
> - if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
> + if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
> + || (mode == OImode && (code == EQ || code == NE)))
No need for the code check here. You have an assert in the code below.
> {
> rtx flag = gen_rtx_REG (CCZmode, FLAGS_REG);
> machine_mode p_mode = GET_MODE_SIZE (mode) == 32 ? V4DImode : V2DImode;
>
> + if (mode == OImode)
> + {
> + op0 = lowpart_subreg (p_mode, force_reg (mode, op0), mode);
> + op1 = lowpart_subreg (p_mode, force_reg (mode, op1), mode);
> + mode = p_mode;
> + }
> +
> gcc_assert (code == EQ || code == NE);
Please put the above hunk after the assert.
> /* Generate XOR since we can't check that one operand is zero vector. */
> tmp = gen_reg_rtx (mode);
> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> index 7b791def542..9514b8e0234 100644
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -26034,10 +26034,14 @@ (define_expand "maskstore<mode><avx512fmaskmodelower>"
> (match_operand:<avx512fmaskmode> 2 "register_operand")))]
> "TARGET_AVX512BW")
>
> +(define_mode_iterator VI48_OI_AVX
> + [(V8SI "TARGET_AVX") (V4DI "TARGET_AVX") (OI "TARGET_AVX")
> + V4SI V2DI])
> +
> (define_expand "cbranch<mode>4"
> [(set (reg:CC FLAGS_REG)
> - (compare:CC (match_operand:VI48_AVX 1 "register_operand")
> - (match_operand:VI48_AVX 2 "nonimmediate_operand")))
> + (compare:CC (match_operand:VI48_OI_AVX 1 "register_operand")
> + (match_operand:VI48_OI_AVX 2 "nonimmediate_operand")))
> (set (pc) (if_then_else
> (match_operator 0 "bt_comparison_operator"
> [(reg:CC FLAGS_REG) (const_int 0)])
Please rather put the new cbranchoi4 expander in i386.md.
> diff --git a/gcc/testsuite/gcc.target/i386/pr104610.c b/gcc/testsuite/gcc.target/i386/pr104610.c
> new file mode 100644
> index 00000000000..00866238bd7
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr104610.c
> @@ -0,0 +1,15 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -mmove-max=256 -mstore-max=256" } */
> +/* { dg-final { scan-assembler-times {(?n)vptest.*ymm} 1 } } */
> +/* { dg-final { scan-assembler-times {sete} 1 } } */
> +/* { dg-final { scan-assembler-not {(?n)je.*L[0-9]} } } */
> +/* { dg-final { scan-assembler-not {(?n)jne.*L[0-9]} } } */
> +
> +
> +#include<stdbool.h>
> +__attribute__((target("avx")))
> +bool f256(char *a)
Use _Bool istead and simply pass -mavx to dg-options.
Uros.
> +{
> + char t[] = "0123456789012345678901234567890";
> + return __builtin_memcmp(a, &t[0], sizeof(t)) == 0;
> +}
> --
> 2.18.1
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] Expand __builtin_memcmp_eq with ptest for OImode.
2022-05-16 9:10 ` Uros Bizjak
@ 2022-05-17 1:33 ` Hongtao Liu
2022-05-17 10:03 ` Uros Bizjak
0 siblings, 1 reply; 14+ messages in thread
From: Hongtao Liu @ 2022-05-17 1:33 UTC (permalink / raw)
To: Uros Bizjak; +Cc: liuhongt, gcc-patches
[-- Attachment #1: Type: text/plain, Size: 4414 bytes --]
On Mon, May 16, 2022 at 5:21 PM Uros Bizjak via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> On Sat, May 7, 2022 at 7:05 AM liuhongt <hongtao.liu@intel.com> wrote:
> >
> > This is adjusted patch only for OImode.
> >
> > Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
> > Ok for trunk?
> >
> > gcc/ChangeLog:
> >
> > PR target/104610
> > * config/i386/i386-expand.cc (ix86_expand_branch): Use ptest
> > for QImode when code is EQ or NE.
> > * config/i386/sse.md (cbranch<mode>4): Extend to OImode.
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.target/i386/pr104610.c: New test.
> > ---
> > gcc/config/i386/i386-expand.cc | 10 +++++++++-
> > gcc/config/i386/sse.md | 8 ++++++--
> > gcc/testsuite/gcc.target/i386/pr104610.c | 15 +++++++++++++++
> > 3 files changed, 30 insertions(+), 3 deletions(-)
> > create mode 100644 gcc/testsuite/gcc.target/i386/pr104610.c
> >
> > diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
> > index bc806ffa283..c2f8776102c 100644
> > --- a/gcc/config/i386/i386-expand.cc
> > +++ b/gcc/config/i386/i386-expand.cc
> > @@ -2267,11 +2267,19 @@ ix86_expand_branch (enum rtx_code code, rtx op0, rtx op1, rtx label)
> >
> > /* Handle special case - vector comparsion with boolean result, transform
> > it using ptest instruction. */
> > - if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
> > + if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
> > + || (mode == OImode && (code == EQ || code == NE)))
>
> No need for the code check here. You have an assert in the code below.
>
Changed.
I mistakenly saw the QImode as OImode, I thought OImode other compare
code can also handle.
> > {
> > rtx flag = gen_rtx_REG (CCZmode, FLAGS_REG);
> > machine_mode p_mode = GET_MODE_SIZE (mode) == 32 ? V4DImode : V2DImode;
> >
> > + if (mode == OImode)
> > + {
> > + op0 = lowpart_subreg (p_mode, force_reg (mode, op0), mode);
> > + op1 = lowpart_subreg (p_mode, force_reg (mode, op1), mode);
> > + mode = p_mode;
> > + }
> > +
> > gcc_assert (code == EQ || code == NE);
>
> Please put the above hunk after the assert.
Changed.
>
> > /* Generate XOR since we can't check that one operand is zero vector. */
> > tmp = gen_reg_rtx (mode);
> > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> > index 7b791def542..9514b8e0234 100644
> > --- a/gcc/config/i386/sse.md
> > +++ b/gcc/config/i386/sse.md
> > @@ -26034,10 +26034,14 @@ (define_expand "maskstore<mode><avx512fmaskmodelower>"
> > (match_operand:<avx512fmaskmode> 2 "register_operand")))]
> > "TARGET_AVX512BW")
> >
> > +(define_mode_iterator VI48_OI_AVX
> > + [(V8SI "TARGET_AVX") (V4DI "TARGET_AVX") (OI "TARGET_AVX")
> > + V4SI V2DI])
> > +
> > (define_expand "cbranch<mode>4"
> > [(set (reg:CC FLAGS_REG)
> > - (compare:CC (match_operand:VI48_AVX 1 "register_operand")
> > - (match_operand:VI48_AVX 2 "nonimmediate_operand")))
> > + (compare:CC (match_operand:VI48_OI_AVX 1 "register_operand")
> > + (match_operand:VI48_OI_AVX 2 "nonimmediate_operand")))
> > (set (pc) (if_then_else
> > (match_operator 0 "bt_comparison_operator"
> > [(reg:CC FLAGS_REG) (const_int 0)])
>
> Please rather put the new cbranchoi4 expander in i386.md.
Good idea, changed.
>
> > diff --git a/gcc/testsuite/gcc.target/i386/pr104610.c b/gcc/testsuite/gcc.target/i386/pr104610.c
> > new file mode 100644
> > index 00000000000..00866238bd7
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/i386/pr104610.c
> > @@ -0,0 +1,15 @@
> > +/* { dg-do compile } */
> > +/* { dg-options "-O2 -mmove-max=256 -mstore-max=256" } */
> > +/* { dg-final { scan-assembler-times {(?n)vptest.*ymm} 1 } } */
> > +/* { dg-final { scan-assembler-times {sete} 1 } } */
> > +/* { dg-final { scan-assembler-not {(?n)je.*L[0-9]} } } */
> > +/* { dg-final { scan-assembler-not {(?n)jne.*L[0-9]} } } */
> > +
> > +
> > +#include<stdbool.h>
> > +__attribute__((target("avx")))
> > +bool f256(char *a)
>
> Use _Bool istead and simply pass -mavx to dg-options.
>
Changed.
> Uros.
>
> > +{
> > + char t[] = "0123456789012345678901234567890";
> > + return __builtin_memcmp(a, &t[0], sizeof(t)) == 0;
> > +}
> > --
> > 2.18.1
> >
Here's the updated patch.
--
BR,
Hongtao
[-- Attachment #2: v2-0001-Expand-__builtin_memcmp_eq-with-ptest-for-OImode.patch --]
[-- Type: application/octet-stream, Size: 3365 bytes --]
From da9f359a0cd3915ffa42ad6cf192a18788015136 Mon Sep 17 00:00:00 2001
From: liuhongt <hongtao.liu@intel.com>
Date: Tue, 1 Mar 2022 13:41:52 +0800
Subject: [PATCH v2] Expand __builtin_memcmp_eq with ptest for OImode.
gcc/ChangeLog:
PR target/104610
* config/i386/i386-expand.cc (ix86_expand_branch): Use ptest
for QImode when code is EQ or NE.
* config/i386/i386.md (cbranchoi4): New expander.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr104610.c: New test.
---
gcc/config/i386/i386-expand.cc | 9 ++++++++-
gcc/config/i386/i386.md | 16 ++++++++++++++++
gcc/testsuite/gcc.target/i386/pr104610.c | 13 +++++++++++++
3 files changed, 37 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/i386/pr104610.c
diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index 0fd3028c205..b26c626a48a 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -2267,12 +2267,19 @@ ix86_expand_branch (enum rtx_code code, rtx op0, rtx op1, rtx label)
/* Handle special case - vector comparsion with boolean result, transform
it using ptest instruction. */
- if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
+ if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
+ || mode == OImode)
{
rtx flag = gen_rtx_REG (CCZmode, FLAGS_REG);
machine_mode p_mode = GET_MODE_SIZE (mode) == 32 ? V4DImode : V2DImode;
gcc_assert (code == EQ || code == NE);
+ if (mode == OImode)
+ {
+ op0 = lowpart_subreg (p_mode, force_reg (mode, op0), mode);
+ op1 = lowpart_subreg (p_mode, force_reg (mode, op1), mode);
+ mode = p_mode;
+ }
/* Generate XOR since we can't check that one operand is zero vector. */
tmp = gen_reg_rtx (mode);
emit_insn (gen_rtx_SET (tmp, gen_rtx_XOR (mode, op0, op1)));
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index f9c06ff302a..76bb56542da 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -1338,6 +1338,22 @@ (define_expand "cbranch<mode>4"
DONE;
})
+(define_expand "cbranchoi4"
+ [(set (reg:CC FLAGS_REG)
+ (compare:CC (match_operand:OI 1 "nonimmediate_operand")
+ (match_operand:OI 2 "nonimmediate_operand")))
+ (set (pc) (if_then_else
+ (match_operator 0 "bt_comparison_operator"
+ [(reg:CC FLAGS_REG) (const_int 0)])
+ (label_ref (match_operand 3))
+ (pc)))]
+ "TARGET_AVX"
+{
+ ix86_expand_branch (GET_CODE (operands[0]),
+ operands[1], operands[2], operands[3]);
+ DONE;
+})
+
(define_expand "cstore<mode>4"
[(set (reg:CC FLAGS_REG)
(compare:CC (match_operand:SWIM 2 "nonimmediate_operand")
diff --git a/gcc/testsuite/gcc.target/i386/pr104610.c b/gcc/testsuite/gcc.target/i386/pr104610.c
new file mode 100644
index 00000000000..fe39cbe5b8a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr104610.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx -mmove-max=256 -mstore-max=256" } */
+/* { dg-final { scan-assembler-times {(?n)vptest.*ymm} 1 } } */
+/* { dg-final { scan-assembler-times {sete} 1 } } */
+/* { dg-final { scan-assembler-not {(?n)je.*L[0-9]} } } */
+/* { dg-final { scan-assembler-not {(?n)jne.*L[0-9]} } } */
+
+
+_Bool f256(char *a)
+{
+ char t[] = "0123456789012345678901234567890";
+ return __builtin_memcmp(a, &t[0], sizeof(t)) == 0;
+}
--
2.18.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] Expand __builtin_memcmp_eq with ptest for OImode.
2022-05-17 1:33 ` Hongtao Liu
@ 2022-05-17 10:03 ` Uros Bizjak
2022-05-18 2:53 ` Hongtao Liu
0 siblings, 1 reply; 14+ messages in thread
From: Uros Bizjak @ 2022-05-17 10:03 UTC (permalink / raw)
To: Hongtao Liu; +Cc: liuhongt, gcc-patches
On Tue, May 17, 2022 at 3:33 AM Hongtao Liu <crazylht@gmail.com> wrote:
>
> On Mon, May 16, 2022 at 5:21 PM Uros Bizjak via Gcc-patches
> <gcc-patches@gcc.gnu.org> wrote:
> >
> > On Sat, May 7, 2022 at 7:05 AM liuhongt <hongtao.liu@intel.com> wrote:
> > >
> > > This is adjusted patch only for OImode.
> > >
> > > Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
> > > Ok for trunk?
> > >
> > > gcc/ChangeLog:
> > >
> > > PR target/104610
> > > * config/i386/i386-expand.cc (ix86_expand_branch): Use ptest
> > > for QImode when code is EQ or NE.
> > > * config/i386/sse.md (cbranch<mode>4): Extend to OImode.
> > >
> > > gcc/testsuite/ChangeLog:
> > >
> > > * gcc.target/i386/pr104610.c: New test.
> > > ---
> > > gcc/config/i386/i386-expand.cc | 10 +++++++++-
> > > gcc/config/i386/sse.md | 8 ++++++--
> > > gcc/testsuite/gcc.target/i386/pr104610.c | 15 +++++++++++++++
> > > 3 files changed, 30 insertions(+), 3 deletions(-)
> > > create mode 100644 gcc/testsuite/gcc.target/i386/pr104610.c
> > >
> > > diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
> > > index bc806ffa283..c2f8776102c 100644
> > > --- a/gcc/config/i386/i386-expand.cc
> > > +++ b/gcc/config/i386/i386-expand.cc
> > > @@ -2267,11 +2267,19 @@ ix86_expand_branch (enum rtx_code code, rtx op0, rtx op1, rtx label)
> > >
> > > /* Handle special case - vector comparsion with boolean result, transform
> > > it using ptest instruction. */
> > > - if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
> > > + if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
> > > + || (mode == OImode && (code == EQ || code == NE)))
> >
> > No need for the code check here. You have an assert in the code below.
> >
> Changed.
> I mistakenly saw the QImode as OImode, I thought OImode other compare
> code can also handle.
> > > {
> > > rtx flag = gen_rtx_REG (CCZmode, FLAGS_REG);
> > > machine_mode p_mode = GET_MODE_SIZE (mode) == 32 ? V4DImode : V2DImode;
> > >
> > > + if (mode == OImode)
> > > + {
> > > + op0 = lowpart_subreg (p_mode, force_reg (mode, op0), mode);
> > > + op1 = lowpart_subreg (p_mode, force_reg (mode, op1), mode);
> > > + mode = p_mode;
> > > + }
> > > +
> > > gcc_assert (code == EQ || code == NE);
> >
> > Please put the above hunk after the assert.
> Changed.
> >
> > > /* Generate XOR since we can't check that one operand is zero vector. */
> > > tmp = gen_reg_rtx (mode);
> > > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> > > index 7b791def542..9514b8e0234 100644
> > > --- a/gcc/config/i386/sse.md
> > > +++ b/gcc/config/i386/sse.md
> > > @@ -26034,10 +26034,14 @@ (define_expand "maskstore<mode><avx512fmaskmodelower>"
> > > (match_operand:<avx512fmaskmode> 2 "register_operand")))]
> > > "TARGET_AVX512BW")
> > >
> > > +(define_mode_iterator VI48_OI_AVX
> > > + [(V8SI "TARGET_AVX") (V4DI "TARGET_AVX") (OI "TARGET_AVX")
> > > + V4SI V2DI])
> > > +
> > > (define_expand "cbranch<mode>4"
> > > [(set (reg:CC FLAGS_REG)
> > > - (compare:CC (match_operand:VI48_AVX 1 "register_operand")
> > > - (match_operand:VI48_AVX 2 "nonimmediate_operand")))
> > > + (compare:CC (match_operand:VI48_OI_AVX 1 "register_operand")
> > > + (match_operand:VI48_OI_AVX 2 "nonimmediate_operand")))
> > > (set (pc) (if_then_else
> > > (match_operator 0 "bt_comparison_operator"
> > > [(reg:CC FLAGS_REG) (const_int 0)])
> >
> > Please rather put the new cbranchoi4 expander in i386.md.
> Good idea, changed.
> >
> > > diff --git a/gcc/testsuite/gcc.target/i386/pr104610.c b/gcc/testsuite/gcc.target/i386/pr104610.c
> > > new file mode 100644
> > > index 00000000000..00866238bd7
> > > --- /dev/null
> > > +++ b/gcc/testsuite/gcc.target/i386/pr104610.c
> > > @@ -0,0 +1,15 @@
> > > +/* { dg-do compile } */
> > > +/* { dg-options "-O2 -mmove-max=256 -mstore-max=256" } */
> > > +/* { dg-final { scan-assembler-times {(?n)vptest.*ymm} 1 } } */
> > > +/* { dg-final { scan-assembler-times {sete} 1 } } */
> > > +/* { dg-final { scan-assembler-not {(?n)je.*L[0-9]} } } */
> > > +/* { dg-final { scan-assembler-not {(?n)jne.*L[0-9]} } } */
> > > +
> > > +
> > > +#include<stdbool.h>
> > > +__attribute__((target("avx")))
> > > +bool f256(char *a)
> >
> > Use _Bool istead and simply pass -mavx to dg-options.
> >
> Changed.
> > Uros.
> >
> > > +{
> > > + char t[] = "0123456789012345678901234567890";
> > > + return __builtin_memcmp(a, &t[0], sizeof(t)) == 0;
> > > +}
> > > --
> > > 2.18.1
> > >
>
>
> Here's the updated patch.
gcc_assert (code == EQ || code == NE);
+ if (mode == OImode)
Please add one line of vertical space in the code above.
OK with that change.
Thanks,
Uros.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] Expand __builtin_memcmp_eq with ptest for OImode.
2022-05-17 10:03 ` Uros Bizjak
@ 2022-05-18 2:53 ` Hongtao Liu
0 siblings, 0 replies; 14+ messages in thread
From: Hongtao Liu @ 2022-05-18 2:53 UTC (permalink / raw)
To: Uros Bizjak; +Cc: liuhongt, gcc-patches
On Tue, May 17, 2022 at 6:03 PM Uros Bizjak <ubizjak@gmail.com> wrote:
>
> On Tue, May 17, 2022 at 3:33 AM Hongtao Liu <crazylht@gmail.com> wrote:
> >
> > On Mon, May 16, 2022 at 5:21 PM Uros Bizjak via Gcc-patches
> > <gcc-patches@gcc.gnu.org> wrote:
> > >
> > > On Sat, May 7, 2022 at 7:05 AM liuhongt <hongtao.liu@intel.com> wrote:
> > > >
> > > > This is adjusted patch only for OImode.
> > > >
> > > > Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
> > > > Ok for trunk?
> > > >
> > > > gcc/ChangeLog:
> > > >
> > > > PR target/104610
> > > > * config/i386/i386-expand.cc (ix86_expand_branch): Use ptest
> > > > for QImode when code is EQ or NE.
> > > > * config/i386/sse.md (cbranch<mode>4): Extend to OImode.
> > > >
> > > > gcc/testsuite/ChangeLog:
> > > >
> > > > * gcc.target/i386/pr104610.c: New test.
> > > > ---
> > > > gcc/config/i386/i386-expand.cc | 10 +++++++++-
> > > > gcc/config/i386/sse.md | 8 ++++++--
> > > > gcc/testsuite/gcc.target/i386/pr104610.c | 15 +++++++++++++++
> > > > 3 files changed, 30 insertions(+), 3 deletions(-)
> > > > create mode 100644 gcc/testsuite/gcc.target/i386/pr104610.c
> > > >
> > > > diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
> > > > index bc806ffa283..c2f8776102c 100644
> > > > --- a/gcc/config/i386/i386-expand.cc
> > > > +++ b/gcc/config/i386/i386-expand.cc
> > > > @@ -2267,11 +2267,19 @@ ix86_expand_branch (enum rtx_code code, rtx op0, rtx op1, rtx label)
> > > >
> > > > /* Handle special case - vector comparsion with boolean result, transform
> > > > it using ptest instruction. */
> > > > - if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
> > > > + if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
> > > > + || (mode == OImode && (code == EQ || code == NE)))
> > >
> > > No need for the code check here. You have an assert in the code below.
> > >
> > Changed.
> > I mistakenly saw the QImode as OImode, I thought OImode other compare
> > code can also handle.
> > > > {
> > > > rtx flag = gen_rtx_REG (CCZmode, FLAGS_REG);
> > > > machine_mode p_mode = GET_MODE_SIZE (mode) == 32 ? V4DImode : V2DImode;
> > > >
> > > > + if (mode == OImode)
> > > > + {
> > > > + op0 = lowpart_subreg (p_mode, force_reg (mode, op0), mode);
> > > > + op1 = lowpart_subreg (p_mode, force_reg (mode, op1), mode);
> > > > + mode = p_mode;
> > > > + }
> > > > +
> > > > gcc_assert (code == EQ || code == NE);
> > >
> > > Please put the above hunk after the assert.
> > Changed.
> > >
> > > > /* Generate XOR since we can't check that one operand is zero vector. */
> > > > tmp = gen_reg_rtx (mode);
> > > > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> > > > index 7b791def542..9514b8e0234 100644
> > > > --- a/gcc/config/i386/sse.md
> > > > +++ b/gcc/config/i386/sse.md
> > > > @@ -26034,10 +26034,14 @@ (define_expand "maskstore<mode><avx512fmaskmodelower>"
> > > > (match_operand:<avx512fmaskmode> 2 "register_operand")))]
> > > > "TARGET_AVX512BW")
> > > >
> > > > +(define_mode_iterator VI48_OI_AVX
> > > > + [(V8SI "TARGET_AVX") (V4DI "TARGET_AVX") (OI "TARGET_AVX")
> > > > + V4SI V2DI])
> > > > +
> > > > (define_expand "cbranch<mode>4"
> > > > [(set (reg:CC FLAGS_REG)
> > > > - (compare:CC (match_operand:VI48_AVX 1 "register_operand")
> > > > - (match_operand:VI48_AVX 2 "nonimmediate_operand")))
> > > > + (compare:CC (match_operand:VI48_OI_AVX 1 "register_operand")
> > > > + (match_operand:VI48_OI_AVX 2 "nonimmediate_operand")))
> > > > (set (pc) (if_then_else
> > > > (match_operator 0 "bt_comparison_operator"
> > > > [(reg:CC FLAGS_REG) (const_int 0)])
> > >
> > > Please rather put the new cbranchoi4 expander in i386.md.
> > Good idea, changed.
> > >
> > > > diff --git a/gcc/testsuite/gcc.target/i386/pr104610.c b/gcc/testsuite/gcc.target/i386/pr104610.c
> > > > new file mode 100644
> > > > index 00000000000..00866238bd7
> > > > --- /dev/null
> > > > +++ b/gcc/testsuite/gcc.target/i386/pr104610.c
> > > > @@ -0,0 +1,15 @@
> > > > +/* { dg-do compile } */
> > > > +/* { dg-options "-O2 -mmove-max=256 -mstore-max=256" } */
> > > > +/* { dg-final { scan-assembler-times {(?n)vptest.*ymm} 1 } } */
> > > > +/* { dg-final { scan-assembler-times {sete} 1 } } */
> > > > +/* { dg-final { scan-assembler-not {(?n)je.*L[0-9]} } } */
> > > > +/* { dg-final { scan-assembler-not {(?n)jne.*L[0-9]} } } */
> > > > +
> > > > +
> > > > +#include<stdbool.h>
> > > > +__attribute__((target("avx")))
> > > > +bool f256(char *a)
> > >
> > > Use _Bool istead and simply pass -mavx to dg-options.
> > >
> > Changed.
> > > Uros.
> > >
> > > > +{
> > > > + char t[] = "0123456789012345678901234567890";
> > > > + return __builtin_memcmp(a, &t[0], sizeof(t)) == 0;
> > > > +}
> > > > --
> > > > 2.18.1
> > > >
> >
> >
> > Here's the updated patch.
>
>
> gcc_assert (code == EQ || code == NE);
> + if (mode == OImode)
>
> Please add one line of vertical space in the code above.
>
> OK with that change.
Thanks for the review, commited.
>
> Thanks,
> Uros.
--
BR,
Hongtao
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2022-05-18 2:53 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-05 7:37 [PATCH] Expand __builtin_memcmp_eq with ptest for OI/TImode liuhongt
2022-05-05 7:37 ` Hongtao Liu
2022-05-05 7:49 ` Richard Biener
2022-05-05 8:08 ` Uros Bizjak
2022-05-05 8:21 ` Uros Bizjak
2022-05-05 8:22 ` Hongtao Liu
2022-05-05 8:30 ` Uros Bizjak
2022-05-07 5:05 ` [PATCH] Expand __builtin_memcmp_eq with ptest for OImode liuhongt
2022-05-09 0:57 ` Hongtao Liu
2022-05-16 1:47 ` Hongtao Liu
2022-05-16 9:10 ` Uros Bizjak
2022-05-17 1:33 ` Hongtao Liu
2022-05-17 10:03 ` Uros Bizjak
2022-05-18 2:53 ` Hongtao Liu
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