From: Uros Bizjak <ubizjak@gmail.com>
To: Roger Sayle <roger@nextmovesoftware.com>
Cc: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>,
Segher Boessenkool <segher@kernel.crashing.org>
Subject: Re: [x86 PATCH] Fun with flags: Adding stc/clc instructions to i386.md.
Date: Fri, 8 Jul 2022 09:59:16 +0200 [thread overview]
Message-ID: <CAFULd4bUSXHJDoFy9QUMu7GP9+ioO2jyPX3W2ZtfmrQ8A_FL-Q@mail.gmail.com> (raw)
In-Reply-To: <003b01d8929a$70be2cc0$523a8640$@nextmovesoftware.com>
On Fri, Jul 8, 2022 at 9:15 AM Roger Sayle <roger@nextmovesoftware.com> wrote:
>
>
> This patch adds support for x86's single-byte encoded stc (set carry flag)
> and clc (clear carry flag) instructions to i386.md.
>
> The motivating example is the simple code snippet:
>
> unsigned int foo (unsigned int a, unsigned int b, unsigned int *c)
> {
> return __builtin_ia32_addcarryx_u32 (1, a, b, c);
> }
>
> which uses the target built-in to generate an adc instruction, adding
> together A and B with the incoming carry flag already set. Currently
> for this mainline GCC generates (with -O2):
>
> movl $1, %eax
> addb $-1, %al
> adcl %esi, %edi
> setc %al
> movl %edi, (%rdx)
> movzbl %al, %eax
> ret
>
> where the first two instructions (to load 1 into a byte register and
> then add 255 to it) are the idiom used to set the carry flag. This
> is a little inefficient as x86 has a "stc" instruction for precisely
> this purpose. With the attached patch we now generate:
>
> stc
> adcl %esi, %edi
> setc %al
> movl %edi, (%rdx)
> movzbl %al, %eax
> ret
Please note that STC/CLC is quite unoptimal on some older
architectures. For example, Pentium4 has a latency of 10 due to false
dependency of flags [1].
[1] https://agner.org/optimize/instruction_tables.pdf
Uros.
next prev parent reply other threads:[~2022-07-08 7:59 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-08 7:14 Roger Sayle
2022-07-08 7:23 ` Uros Bizjak
2022-07-08 7:59 ` Uros Bizjak [this message]
2022-07-08 21:08 ` Segher Boessenkool
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