From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qv1-xf2a.google.com (mail-qv1-xf2a.google.com [IPv6:2607:f8b0:4864:20::f2a]) by sourceware.org (Postfix) with ESMTPS id 325903858C54 for ; Sat, 13 Aug 2022 09:57:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 325903858C54 Received: by mail-qv1-xf2a.google.com with SMTP id l18so2249515qvt.13 for ; Sat, 13 Aug 2022 02:57:37 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc; bh=8z6YTpETFsDSUWnCigcq8jHwXrl9fojKNkKRYMH/b5k=; b=pmlmJXpg6g+udduBYMz4/ExTwA+j2kV2360GzHTF3rX9c5CYOyWN+BcHQw5f15nvQ9 neR2axGTbq+9LrA3AFSc773iytfqRPZQWWlpzJ1UQaZ7+Mb48mozWu+Ew+E42d/JIOUJ seJGzRkPsmTJ1Vo0JRhfFWFlnoY1+2Q/5y47hapTK5OudvER91B3E477KPOmFkJJ9ij+ w1rKpVK0TgT8/zVrNiQEfCGUFkWzl8NGS+qrU7FcCH+/EjMd4ijX842nO4M/zKbRYbLj zHFLqAbVqCC+cXETjlKLepffUBv3N+ZPJMyjDO9eV/8XW9BzL71+TYXCxIO+Ir2CgnU2 Co+Q== X-Gm-Message-State: ACgBeo1HcCRykD5fLkrs+mZg7rZVMSaOUEdbV4F/SDl7wLYkqhidhuhG MfhG3M4r8l7ZbdbAVNraikTWR7znWZ3dvCOrD+MDYdGXU7E= X-Google-Smtp-Source: AA6agR7CK1haXX3+6dIQ5RqRLd9H2bvIZzYx/oPCS9ZEtQ22t0jXGzmxy6aM+TfPamxU3+hu6t0GpGr24MlnIOEaUvU= X-Received: by 2002:ad4:4b30:0:b0:476:f037:8a2 with SMTP id s16-20020ad44b30000000b00476f03708a2mr6779831qvw.2.1660384656365; Sat, 13 Aug 2022 02:57:36 -0700 (PDT) MIME-Version: 1.0 References: <037701d8a8fa$4f65ed80$ee31c880$@nextmovesoftware.com> <008101d8ae91$ef2ca100$cd85e300$@nextmovesoftware.com> In-Reply-To: <008101d8ae91$ef2ca100$cd85e300$@nextmovesoftware.com> From: Uros Bizjak Date: Sat, 13 Aug 2022 11:57:36 +0200 Message-ID: Subject: Re: [x86 PATCH take #2] Move V1TI shift/rotate lowering from expand to pre-reload split. To: Roger Sayle Cc: gcc-patches@gcc.gnu.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-2.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 13 Aug 2022 09:57:38 -0000 On Fri, Aug 12, 2022 at 11:24 PM Roger Sayle w= rote: > > > Hi Uros, > As requested, here's an updated version of my patch that introduces a new > const_0_to_255_not_mul_8_operand as you've requested. I think in this > instance, having mutually exclusive patterns that can appear in any order= , > without imposing implicit ordering constraints, is slightly preferable, > especially as (thanks to STV) some related patterns may appear in > sse.md and others appear in i386.md (making ordering tricky). > > This patch has been retested on x86_64-pc-linux-gnu with make bootstrap > and make -k check, both with and without --target_board=3Dunix{-m32}, > with no new failures. Ok for mainline? > > > 2022-08-12 Roger Sayle > Uro=C5=A1 Bizjak > > gcc/ChangeLog > * config/i386/predicates.md (const_0_to_255_not_mul_8_operand): > New predicate for values between 0/1 and 255, not multiples of 8. > * config/i386/sse.md (ashlv1ti3): Delay lowering of logical left > shifts by constant bit counts. > (*ashlvti3_internal): New define_insn_and_split that lowers > logical left shifts by constant bit counts, that aren't multiples > of 8, before reload. > (lshrv1ti3): Delay lowering of logical right shifts by constant. > (*lshrv1ti3_internal): New define_insn_and_split that lowers > logical right shifts by constant bit counts, that aren't multiple= s > of 8, before reload. > (ashrv1ti3):: Delay lowering of arithmetic right shifts by > constant bit counts. > (*ashrv1ti3_internal): New define_insn_and_split that lowers > arithmetic right shifts by constant bit counts before reload. > (rotlv1ti3): Delay lowering of rotate left by constant. > (*rotlv1ti3_internal): New define_insn_and_split that lowers > rotate left by constant bits counts before reload. > (rotrv1ti3): Delay lowering of rotate right by constant. > (*rotrv1ti3_internal): New define_insn_and_split that lowers > rotate right by constant bits counts before reload. OK with a small nit: + "TARGET_SSE2 + && TARGET_64BIT Please put these target options to one line, as in many examples throuhout i386.md Thanks, Uros.