From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw1-x1132.google.com (mail-yw1-x1132.google.com [IPv6:2607:f8b0:4864:20::1132]) by sourceware.org (Postfix) with ESMTPS id DCBB7385841D for ; Mon, 14 Nov 2022 07:57:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org DCBB7385841D Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-yw1-x1132.google.com with SMTP id 00721157ae682-36ad4cf9132so98746197b3.6 for ; Sun, 13 Nov 2022 23:57:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=c0eNP+s21rgdjCH+ApYOumm6tyeWooAXirYDepM6w8U=; b=EaCE57MJrWbtRaudwPxKVsjxQC+P97Y6AnwO1/pKpYkwSeKMJCggTAVjLgrgUGojbo Cx7CTQe0Z5CgTjUW/NRdrAqScgMgU6I82tSMdtUBuoRrQPTEIc2pYA0M88DT6y3bis64 C3kQoKvNLPBBPXorOjUAID24vh4q1B1ZAmx2tFrJ3NGPde1+1WHB5DJXvvNpe2v9Tiu9 zblAwEpE5gy6ZoGP8z9f0VF9orB/LS6IQzAdJL4QZKh1gSD1nTpiGm0Rg1Tc8qDDQPgH 29QWAqUx501Gc4DBeH7Fsfa7C5mchFPMgenpgLWkUsUhkyZEmWee4DinTbbmxIfbaSyC jfaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=c0eNP+s21rgdjCH+ApYOumm6tyeWooAXirYDepM6w8U=; b=gM0NvDMwzDCP6yCLT0MAsMI6JLT7aiCqe2LL5DyhFXhv9pVOfPrzmkDYKKcIOPF1Oz N2lvfmjZN5K7+cneDO96uRCsWLl480JvDEE+AJxSufeeuA1pO/PKXLgxCugZZcboiLfE WjIukVIj9D9x96mIy3I6HTTBaZqTVQ+JSs+CV7n2iaPa6UHVem1aryLtX9iT3CEYDG+w Y8BPOsPh8/DzMci3kLOM0lV9XRaERB4kbjfXImiuVprIctuosvn9VWXooZjbkY3HHf/T g14zOCHjp5Y37BEExDl/EvTIhMe+JboTAatBl1zfnAuITpajuCwNgSGgdBi9ylAi0qvG IREQ== X-Gm-Message-State: ANoB5plOLqq3yI15gIZuL4S0jQYsHmN0gAA0QgjKWnhq/XgGqhG7XquV v0vOtxUeLDOJZHvjhi1ggtOcKLwr72dEGfCxGJ8= X-Google-Smtp-Source: AA0mqf5ZyGH18pONLxB8TB2wxiPLHSFUm+mJqRn+zwt3/ToDYPX0fnIPI0BtQbfqnBMDD89pAxaV2pLJNmhu7fWwdZc= X-Received: by 2002:a81:a04f:0:b0:381:49e8:aad4 with SMTP id x76-20020a81a04f000000b0038149e8aad4mr3307988ywg.495.1668412640099; Sun, 13 Nov 2022 23:57:20 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Uros Bizjak Date: Mon, 14 Nov 2022 08:57:09 +0100 Message-ID: Subject: Re: [PATCH] i386: Emit 16b atomics inline with -m64 -mcx16 -mavx [PR104688] To: Jakub Jelinek Cc: gcc-patches@gcc.gnu.org, Florian Weimer , "H.J. Lu" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-1.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, Nov 14, 2022 at 8:52 AM Jakub Jelinek wrote: > > Hi! > > Working virtually out of Baker Island. > > Given > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688#c10 > the following patch implements atomic load/store (and therefore also > enabling compare and exchange) for -m64 -mcx16 -mavx. > > Ok for trunk if it passes bootstrap/regtest? We only have guarantee from Intel and AMD, there can be other vendors. Uros. > > 2022-11-13 Jakub Jelinek > > PR target/104688 > * config/i386/sync.md (atomic_loadti, atomic_storeti): New > define_expand patterns. > (atomic_loadti_1, atomic_storeti_1): New define_insn patterns. > > * gcc.target/i386/pr104688-1.c: New test. > * gcc.target/i386/pr104688-2.c: New test. > * gcc.target/i386/pr104688-3.c: New test. > > --- gcc/config/i386/sync.md.jj 2022-11-07 20:54:37.259400942 -1200 > +++ gcc/config/i386/sync.md 2022-11-13 19:27:22.977987355 -1200 > @@ -225,6 +225,31 @@ (define_insn_and_split "atomic_loaddi_fp > DONE; > }) > > +;; Intel SDM guarantees that 16-byte VMOVDQA on 16-byte aligned address > +;; is atomic. AMD will give a similar guarantee. > +(define_expand "atomic_loadti" > + [(set (match_operand:TI 0 "register_operand" "=x,Yv") > + (unspec:TI [(match_operand:TI 1 "memory_operand" "m,m") > + (match_operand:SI 2 "const_int_operand")] > + UNSPEC_LDA))] > + "TARGET_64BIT && TARGET_CMPXCHG16B && TARGET_AVX" > +{ > + emit_insn (gen_atomic_loadti_1 (operands[0], operands[1])); > + DONE; > +}) > + > +(define_insn "atomic_loadti_1" > + [(set (match_operand:TI 0 "register_operand" "=x,Yv") > + (unspec:TI [(match_operand:TI 1 "memory_operand" "m,m")] > + UNSPEC_LDA))] > + "TARGET_64BIT && TARGET_CMPXCHG16B && TARGET_AVX" > + "@ > + vmovdqa\t{%1, %0|%0, %1} > + vmovdqa64\t{%1, %0|%0, %1}" > + [(set_attr "type" "ssemov") > + (set_attr "prefix" "vex,evex") > + (set_attr "mode" "TI")]) > + > (define_expand "atomic_store" > [(set (match_operand:ATOMIC 0 "memory_operand") > (unspec:ATOMIC [(match_operand:ATOMIC 1 "nonimmediate_operand") > @@ -276,6 +301,36 @@ (define_insn "atomic_store_1" > "" > "%K2mov{}\t{%1, %0|%0, %1}") > > +(define_expand "atomic_storeti" > + [(set (match_operand:TI 0 "memory_operand") > + (unspec:TI [(match_operand:TI 1 "register_operand") > + (match_operand:SI 2 "const_int_operand")] > + UNSPEC_STA))] > + "TARGET_64BIT && TARGET_CMPXCHG16B && TARGET_AVX" > +{ > + enum memmodel model = memmodel_from_int (INTVAL (operands[2])); > + > + emit_insn (gen_atomic_storeti_1 (operands[0], operands[1], operands[2])); > + > + /* ... followed by an MFENCE, if required. */ > + if (is_mm_seq_cst (model)) > + emit_insn (gen_mem_thread_fence (operands[2])); > + DONE; > +}) > + > +(define_insn "atomic_storeti_1" > + [(set (match_operand:TI 0 "memory_operand" "=m,m") > + (unspec:TI [(match_operand:TI 1 "register_operand" "x,Yv") > + (match_operand:SI 2 "const_int_operand")] > + UNSPEC_STA))] > + "" > + "@ > + %K2vmovdqa\t{%1, %0|%0, %1} > + %K2vmovdqa64\t{%1, %0|%0, %1}" > + [(set_attr "type" "ssemov") > + (set_attr "prefix" "vex,evex") > + (set_attr "mode" "TI")]) > + > (define_insn_and_split "atomic_storedi_fpu" > [(set (match_operand:DI 0 "memory_operand" "=m,m,m") > (unspec:DI [(match_operand:DI 1 "nonimmediate_operand" "x,m,?r")] > --- gcc/testsuite/gcc.target/i386/pr104688-1.c.jj 2022-11-13 19:36:43.251332612 -1200 > +++ gcc/testsuite/gcc.target/i386/pr104688-1.c 2022-11-13 19:40:22.649334650 -1200 > @@ -0,0 +1,34 @@ > +/* PR target/104688 */ > +/* { dg-do compile { target int128 } } */ > +/* { dg-options "-O2 -mno-cx16" } */ > +/* { dg-final { scan-assembler "\t__sync_val_compare_and_swap_16" } } */ > +/* { dg-final { scan-assembler "\t__atomic_load_16" } } */ > +/* { dg-final { scan-assembler "\t__atomic_store_16" } } */ > +/* { dg-final { scan-assembler "\t__atomic_compare_exchange_16" } } */ > + > +__int128 v; > + > +__int128 > +f1 (void) > +{ > + return __sync_val_compare_and_swap (&v, 42, 0); > +} > + > +__int128 > +f2 (void) > +{ > + return __atomic_load_n (&v, __ATOMIC_SEQ_CST); > +} > + > +void > +f3 (__int128 x) > +{ > + __atomic_store_n (&v, 42, __ATOMIC_SEQ_CST); > +} > + > +__int128 > +f4 (void) > +{ > + __int128 y = 42; > + __atomic_compare_exchange_n (&v, &y, 0, 0, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); > +} > --- gcc/testsuite/gcc.target/i386/pr104688-2.c.jj 2022-11-13 19:36:46.513288025 -1200 > +++ gcc/testsuite/gcc.target/i386/pr104688-2.c 2022-11-13 19:40:34.676170305 -1200 > @@ -0,0 +1,34 @@ > +/* PR target/104688 */ > +/* { dg-do compile { target int128 } } */ > +/* { dg-options "-O2 -mno-avx" } */ > +/* { dg-final { scan-assembler "\t__sync_val_compare_and_swap_16" } } */ > +/* { dg-final { scan-assembler "\t__atomic_load_16" } } */ > +/* { dg-final { scan-assembler "\t__atomic_store_16" } } */ > +/* { dg-final { scan-assembler "\t__atomic_compare_exchange_16" } } */ > + > +__int128 v; > + > +__int128 > +f1 (void) > +{ > + return __sync_val_compare_and_swap (&v, 42, 0); > +} > + > +__int128 > +f2 (void) > +{ > + return __atomic_load_n (&v, __ATOMIC_SEQ_CST); > +} > + > +void > +f3 (__int128 x) > +{ > + __atomic_store_n (&v, 42, __ATOMIC_SEQ_CST); > +} > + > +__int128 > +f4 (void) > +{ > + __int128 y = 42; > + __atomic_compare_exchange_n (&v, &y, 0, 0, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); > +} > --- gcc/testsuite/gcc.target/i386/pr104688-3.c.jj 2022-11-13 19:37:00.899091450 -1200 > +++ gcc/testsuite/gcc.target/i386/pr104688-3.c 2022-11-13 19:40:41.984070460 -1200 > @@ -0,0 +1,34 @@ > +/* PR target/104688 */ > +/* { dg-do compile { target int128 } } */ > +/* { dg-options "-O2 -mcx16 -mavx" } */ > +/* { dg-final { scan-assembler-not "\t__sync_val_compare_and_swap_16" } } */ > +/* { dg-final { scan-assembler-not "\t__atomic_load_16" } } */ > +/* { dg-final { scan-assembler-not "\t__atomic_store_16" } } */ > +/* { dg-final { scan-assembler-not "\t__atomic_compare_exchange_16" } } */ > + > +__int128 v; > + > +__int128 > +f1 (void) > +{ > + return __sync_val_compare_and_swap (&v, 42, 0); > +} > + > +__int128 > +f2 (void) > +{ > + return __atomic_load_n (&v, __ATOMIC_SEQ_CST); > +} > + > +void > +f3 (__int128 x) > +{ > + __atomic_store_n (&v, 42, __ATOMIC_SEQ_CST); > +} > + > +__int128 > +f4 (void) > +{ > + __int128 y = 42; > + __atomic_compare_exchange_n (&v, &y, 0, 0, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); > +} > > > Jakub >