From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qv1-xf2a.google.com (mail-qv1-xf2a.google.com [IPv6:2607:f8b0:4864:20::f2a]) by sourceware.org (Postfix) with ESMTPS id 7C0B5382F84F for ; Tue, 28 Jun 2022 15:38:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 7C0B5382F84F Received: by mail-qv1-xf2a.google.com with SMTP id i17so20485326qvo.13 for ; Tue, 28 Jun 2022 08:38:27 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=wAF7CXs1GQy3EHU9XVZUhrth7Ej1Pch2p9OtByr3jKU=; b=iuSyRNRRUcbdZHQGFZp6W7YLfoXeVvZE9GOWdv+/1elIzOFivfH7QtOIIQLWFGr9m3 olYvZmkW/MU+GD6VIHocpButoNM4/LNlkW/4spaIe3ABUTNuiFSb9YNmRjKiTjJgeJpU ebAIz7wTk/Yn/uayFqYUJpLLtXSPldj63DYgwKRjxkcXzuqaouUAV8/omwwK+syv2PMY 5HORDST4o8xHyclu5R24igV7CqJ4U4ILn+XD3/P2kFqV8d+ZGoVzGrm84UV3aXhlHO4E mclOAmQAo6NvUzd7og9eIWdR5Opf5FNevFG/xVNNSACQ4D0afym5hTmHzM020EVk1y4X 1+aQ== X-Gm-Message-State: AJIora/zuuBNx2zVSZoa0ZB0nqbiZq8Zx04cMs/cZhc9Kw+moN6JX6o2 sLB0ALxEl3qedTZTK/6Y+NfXaFD1gZTW5bNgd1VjUimuUKv4gg== X-Google-Smtp-Source: AGRyM1upS5ZQkdDj/JwKLr7Y9ClqnXt/mZSoKznM90BRsKmPHjB2urRPuOyW2VSBf41C8T6FzLsNzYWAgG2pc2okNNw= X-Received: by 2002:ac8:5a83:0:b0:31a:272f:d67d with SMTP id c3-20020ac85a83000000b0031a272fd67dmr8229983qtc.57.1656430706668; Tue, 28 Jun 2022 08:38:26 -0700 (PDT) MIME-Version: 1.0 References: <009501d88ae3$13aeed30$3b0cc790$@nextmovesoftware.com> In-Reply-To: <009501d88ae3$13aeed30$3b0cc790$@nextmovesoftware.com> From: Uros Bizjak Date: Tue, 28 Jun 2022 17:38:15 +0200 Message-ID: Subject: Re: [x86 PATCH] Double word logical operation clean-ups in i386.md. To: Roger Sayle Cc: "gcc-patches@gcc.gnu.org" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=0.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, KAM_SHORT, MEDICAL_SUBJECT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 28 Jun 2022 15:38:29 -0000 On Tue, Jun 28, 2022 at 1:34 PM Roger Sayle wrote: > > > Hi Uros, > As you've requested/suggested, here's a patch that tidies up and > unifies doubleword handling in i386.md; converting all doubleword > splitters for logic operations to post-reload form, generalizing > their define_insn_and_split templates to form (supporting > TARGET_64BIT ? TImode : DImode), and where required tweaking the > corresponding expanders to use SDWIM to support TImode doubleword > operations. These changes incorporate your feedback from > https://gcc.gnu.org/pipermail/gcc-patches/2022-June/596205.html > where I included many/several of these clean-ups, in a patch to > add a new optimization. I agree, it's better to split these out > (this patch), and I'll resubmit the (smaller) optimization patch > as a follow-up. > > This patch has been tested on x86_64-pc-linux-gnu with make bootstrap > and make -k check, both with and without --target_board=unix{-m32}, > with no new failures. Ok for mainline? > > > 2022-06-28 Roger Sayle > > gcc/ChangeLog > * config/i386/i386.md (general_szext_operand): Add TImode > support using x86_64_hilo_general_operand predicate. > (*cmp_doubleword): Use x86_64_hilo_general_operand predicate. > (*add3_doubleword): Improved optimization of zero addition. > (and3): Use SDWIM mode iterator to add support for double > word bit-wise AND in TImode. Use force_reg when double word > immediate operand isn't x86_64_hilo_general_operand. > (and3_doubleword): Generalized from anddi3_doubleword and > converted into a post-reload splitter. > (*andn3_doubleword): Generalized from *andndi3_doubleword. > (define_split): Generalize DImode splitters for andn to . > One splitter for TARGET_BMI, the other for !TARGET_BMI. > (3): Use SDWIM mode iterator to add suppport for > double word bit-wise XOR and bit-wise IOR in TImode. Use > force_reg when double word immediate operand isn't > x86_64_hilo_general_operand. > (*di3_doubleword): Generalized from di3_doubleword. > (one_cmpl2): Use SDWIM mode iterator to add support for > double word bit-wise NOT in TImode. > (one_cmpl2_doubleword): Generalize from one_cmpldi2_doubleword > and converted into a post-reload splitter. (define_expand "and3" - [(set (match_operand:SWIM1248x 0 "nonimmediate_operand") - (and:SWIM1248x (match_operand:SWIM1248x 1 "nonimmediate_operand") - (match_operand:SWIM1248x 2 "")))] + [(set (match_operand:SDWIM 0 "nonimmediate_operand") + (and:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand") + (match_operand:SDWIM 2 "")))] "" { machine_mode mode = mode; - if (mode == DImode && !TARGET_64BIT) - ; - else if (const_int_operand (operands[2], mode) - && register_operand (operands[0], mode) - && !(TARGET_ZERO_EXTEND_WITH_AND - && optimize_function_for_speed_p (cfun))) + if (GET_MODE_SIZE (mode) > UNITS_PER_WORD + && !x86_64_hilo_general_operand (operands[2], mode)) + operands[2] = force_reg (mode, operands[2]); You don't have to do that - when the predicate can't be satisfied, the middle-end pushes the value to a register as a last resort by default. + bool emit_insn_deleted_note_p = false; + + split_double_mode (mode, &operands[0], 3, &operands[0], &operands[3]); if (operands[2] == const0_rtx) emit_move_insn (operands[0], const0_rtx); else if (operands[2] == constm1_rtx) - emit_move_insn (operands[0], operands[1]); + { + if (!rtx_equal_p (operands[0], operands[1])) + emit_move_insn (operands[0], operands[1]); + else + emit_insn_deleted_note_p = true; + } Please note that when operands[2] is an immediate, constraints after reload *guarantee* that operands[1] match operands[0]. So, the insn should always be deleted (I think that this functionality was in your patch - it is unneeded there, too). +(define_insn "*andn3_doubleword" + [(set (match_operand:DWI 0 "register_operand") + (and:DWI + (not:DWI (match_operand:DWI 1 "register_operand")) + (match_operand:DWI 2 "nonimmediate_operand"))) (clobber (reg:CC FLAGS_REG))] - "!TARGET_64BIT && TARGET_STV && TARGET_SSE2 - && ix86_pre_reload_split ()" + "ix86_pre_reload_split ()" "#") Please introduce two ANDN double-word insn-and-split patterns, one for BMI and one for !BMI. The one for BMI should be moved to a post-reload splitter, too. As we figured out, *all* double-word patterns should either be of pre-reload or of post-reload type. (define_split - [(set (match_operand:DI 0 "register_operand") - (and:DI - (not:DI (match_operand:DI 1 "register_operand")) - (match_operand:DI 2 "nonimmediate_operand"))) + [(set (match_operand:DWI 0 "register_operand") + (and:DWI + (not:DWI (match_operand:DWI 1 "register_operand")) + (match_operand:DWI 2 "nonimmediate_operand"))) (clobber (reg:CC FLAGS_REG))] - "!TARGET_64BIT && !TARGET_BMI && TARGET_STV && TARGET_SSE2 + "!TARGET_BMI Without BMI, the ANDN should be split to a double-word NOT + AND before reload (and these two insns are split to single-word operations after reload). This simplifies splitting logic quite a bit. (define_expand "3" - [(set (match_operand:SWIM1248x 0 "nonimmediate_operand") - (any_or:SWIM1248x (match_operand:SWIM1248x 1 "nonimmediate_operand") - (match_operand:SWIM1248x 2 "")))] + [(set (match_operand:SDWIM 0 "nonimmediate_operand") + (any_or:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand") + (match_operand:SDWIM 2 "")))] Use here ... "" - "ix86_expand_binary_operator (, mode, operands); DONE;") +{ -(define_insn_and_split "*di3_doubleword" - [(set (match_operand:DI 0 "nonimmediate_operand" "=ro,r") - (any_or:DI - (match_operand:DI 1 "nonimmediate_operand" "0,0") - (match_operand:DI 2 "x86_64_szext_general_operand" "re,o"))) + if (GET_MODE_SIZE (mode) > UNITS_PER_WORD + && !x86_64_hilo_general_operand (operands[2], mode)) + operands[2] = force_reg (mode, operands[2]); ... to avoid the above fixup. +(define_insn_and_split "*3_doubleword" + [(set (match_operand: 0 "nonimmediate_operand" "=ro,r") + (any_or: + (match_operand: 1 "nonimmediate_operand" "%0,0") + (match_operand: 2 "x86_64_hilo_general_operand" "r,o"))) for consistency. Otherwise OK. Uros.