Add CC clobber to 32-bit vector mode logic insns to allow variants with
general-purpose registers.  Also improve ix86_sse_movcc to emit insn with
CC clobber for narrow vector modes in order to re-enable conditional moves
for 16-bit and 32-bit narrow vector modes with -msse2.

2022-01-12  Uroš Bizjak  <ubizjak@gmail.com>

gcc/ChangeLog:

    PR target/100637
    PR target/103861
    * config/i386/i386-expand.c (ix86_emit_vec_binop): New static function.
    (ix86_expand_sse_movcc): Use ix86_emit_vec_binop instead of gen_rtx_X
    when constructing vector logic RTXes.
    (expand_vec_perm_pshufb2): Ditto.
    * config/i386/mmx.md (negv2qi): Disparage GPR alternative a bit.
    (<plusminus:insn>v2qi3): Ditto.
    (vcond<mode><mode>): Re-enable for TARGET_SSE2.
    (vcondu<mode><mode>): Ditto.
    (vcond_mask_<mode><mode>): Ditto.
    (one_cmpl<VI_32:mode>2): Remove expander.
    (one_cmpl<VI_16_32:mode>2): Rename from one_cmplv2qi.
    Use VI_16_32 mode iterator.
    (one_cmpl<VI_16_32:mode>2 splitters): Use VI_16_32 mode iterator.
    Use lowpart_subreg instead of gen_lowpart to create subreg.
    (*andnot<VI_16_32:mode>3): Merge from "*andnot<VI_32:mode>" and
    "*andnotv2qi3" insn patterns using VI_16_32 mode iterator.
    Disparage GPR alternative a bit.  Add CC clobber.
    (*andnot<VI_16_32:mode>3 splitters): Use VI_16_32 mode iterator.
    Use lowpart_subreg instead of gen_lowpart to create subreg.
    (*<any_logic:code><VI_16_32:mode>3): Merge from
    "*<any_logic:code><VI_32:mode>" and "*<any_logic:code>v2qi3 insn patterns"
    using VI_16_32 mode iterator.  Disparage GPR alternative a bit.
    Add CC clobber.
    (*<any_logic:code><VI_16_32:mode>3 splitters):Use VI_16_32 mode
    iterator.  Use lowpart_subreg instead of gen_lowpart to create subreg.

gcc/testsuite/ChangeLog:

    PR target/100637
    PR target/103861
    * g++.target/i386/pr100637-1b.C (dg-options):
    Use -msse2 instead of -msse4.1.
    * g++.target/i386/pr100637-1w.C (dg-options): Ditto.
    * g++.target/i386/pr103861-1.C (dg-options): Ditto.
    * gcc.target/i386/pr100637-4b.c (dg-options): Ditto.
    * gcc.target/i386/pr103861-4.c (dg-options): Ditto.
    * gcc.target/i386/pr100637-1b.c: Remove scan-assembler
    directives for logic instructions.
    * gcc.target/i386/pr100637-1w.c: Ditto.
    * gcc.target/i386/warn-vect-op-2.c:
    Update dg-warning for vector logic operation.

Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.

Pushed to master.

Uros.