From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qk1-x72b.google.com (mail-qk1-x72b.google.com [IPv6:2607:f8b0:4864:20::72b]) by sourceware.org (Postfix) with ESMTPS id 37B873857C4E for ; Fri, 15 Apr 2022 11:44:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 37B873857C4E Received: by mail-qk1-x72b.google.com with SMTP id 75so6472144qkk.8 for ; Fri, 15 Apr 2022 04:44:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=p/6Yj3xPjTkxh2ozkFdgVYPKyoVY1ZYU0ng9epk9CPs=; b=pIsuHIwYXmuFsCtPfDIVhUHMDCsTh8C3049OTZ36FZUHiy4s2rRe9yEMOZ4rxqfgj+ 2OhVGY66BAoYHYbI+PBLkaYcX8hYnvU2LLQ6+Jk+ufOrfCDCiNHqxJTT797I+EMtJLRc DmZ4aWzNqKJHVcnN90bpRvbDpFhd9/b/tcnXmuMZFWKAR+R/TtVgEZeV8Iw0JnsXONY0 4eE1Czg5lRfYlOHoT9WRu5hbeFBiV7N+muLbU4RqY9oztOrlzazlUKRb/UBJJPpMcl45 bSpvXRutdOLYObZdUndEFavzVCH1Z9QtWqf2NbAezjfUqMeEowrfpAnonHx9lrrri9BC v5PA== X-Gm-Message-State: AOAM532UH/+zKnrZ+slwKYMu2pm+LPnvdL4iwHr2eDzdDBx1nTf3Y6r6 ISYfFZ2R+ZwWAy7L2V7/gzg8Qoc2tsk0NTJnK1g= X-Google-Smtp-Source: ABdhPJy9ECPv+2sBNAthlHaehSlAWsVwRqB5PCqbGl4U85sAlwEtTeIwGAEH5qAewmpMnkGdtkdPyq/60f7wAGnJg6Y= X-Received: by 2002:a37:f50b:0:b0:680:d577:baf6 with SMTP id l11-20020a37f50b000000b00680d577baf6mr5125110qkk.328.1650023062536; Fri, 15 Apr 2022 04:44:22 -0700 (PDT) MIME-Version: 1.0 References: <20220415042942.77387-1-hongyu.wang@intel.com> In-Reply-To: From: Uros Bizjak Date: Fri, 15 Apr 2022 13:44:11 +0200 Message-ID: Subject: Re: [PATCH] i386: Correct target attribute for crc32 intrinsics To: Hongyu Wang Cc: Hongyu Wang , Hongtao Liu , "gcc-patches@gcc.gnu.org" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00, BODY_8BITS, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Apr 2022 11:44:24 -0000 On Fri, Apr 15, 2022 at 10:34 AM Hongyu Wang wrote= : > > > This test should not be changed, it correctly reports ISA mismatch. It > > even passes -mno-crc32. > > The error message changes from "needs isa option -mcrc32" to "target > specific option mismatch" with the #pragma change. > I see many of our intrinsic would throw such error, it has been a long > term issue for intrinsic diagnostic. > > So for this test either I change the dg-error message or the call to > builtin, otherwise it would fail. Please update the dg-error message. OK with the above change. Thanks, Uros. > > Uros Bizjak via Gcc-patches =E4=BA=8E2022=E5=B9= =B44=E6=9C=8815=E6=97=A5=E5=91=A8=E4=BA=94 15:54=E5=86=99=E9=81=93=EF=BC=9A > > > > On Fri, Apr 15, 2022 at 6:30 AM Hongyu Wang wro= te: > > > > > > Hi, > > > > > > Complile _mm_crc32_u8/16/32/64 intrinsics with -mcrc32 > > > would meet target specific option mismatch. Correct target pragma > > > to fix. > > > > > > Bootstrapped/regtest on x86_64-pc-linux-gnu{-m32,}. > > > > > > Ok for master and backport to GCC 11? > > > > > > gcc/ChangeLog: > > > > > > * config/i386/smmintrin.h: Correct target pragma from sse4.1 > > > and sse4.2 to crc32 for crc32 intrinsics. > > > > > > gcc/testsuite/ChangeLog: > > > > > > * gcc.target/i386/crc32-6.c: Adjust to call builtin. > > > * gcc.target/i386/crc32-7.c: New test. > > > --- > > > gcc/config/i386/smmintrin.h | 25 +++++------------- > > > gcc/testsuite/gcc.target/i386/crc32-6.c | 2 +- > > > gcc/testsuite/gcc.target/i386/crc32-7.c | 34 +++++++++++++++++++++++= ++ > > > 3 files changed, 42 insertions(+), 19 deletions(-) > > > create mode 100644 gcc/testsuite/gcc.target/i386/crc32-7.c > > > > > > diff --git a/gcc/config/i386/smmintrin.h b/gcc/config/i386/smmintrin.= h > > > index b42b212300f..eb6a451c10a 100644 > > > --- a/gcc/config/i386/smmintrin.h > > > +++ b/gcc/config/i386/smmintrin.h > > > @@ -810,17 +810,11 @@ _mm_cmpgt_epi64 (__m128i __X, __m128i __Y) > > > > > > #include > > > > > > -#ifndef __SSE4_1__ > > > +#ifndef __CRC32__ > > > #pragma GCC push_options > > > -#pragma GCC target("sse4.1") > > > -#define __DISABLE_SSE4_1__ > > > -#endif /* __SSE4_1__ */ > > > - > > > -#ifndef __SSE4_2__ > > > -#pragma GCC push_options > > > -#pragma GCC target("sse4.2") > > > -#define __DISABLE_SSE4_2__ > > > -#endif /* __SSE4_1__ */ > > > +#pragma GCC target("crc32") > > > +#define __DISABLE_CRC32__ > > > +#endif /* __CRC32__ */ > > > > > > /* Accumulate CRC32 (polynomial 0x11EDC6F41) value. */ > > > extern __inline unsigned int __attribute__((__gnu_inline__, __always= _inline__, __artificial__)) > > > @@ -849,14 +843,9 @@ _mm_crc32_u64 (unsigned long long __C, unsigned = long long __V) > > > } > > > #endif > > > > > > -#ifdef __DISABLE_SSE4_2__ > > > -#undef __DISABLE_SSE4_2__ > > > +#ifdef __DISABLE_CRC32__ > > > +#undef __DISABLE_CRC32__ > > > #pragma GCC pop_options > > > -#endif /* __DISABLE_SSE4_2__ */ > > > - > > > -#ifdef __DISABLE_SSE4_1__ > > > -#undef __DISABLE_SSE4_1__ > > > -#pragma GCC pop_options > > > -#endif /* __DISABLE_SSE4_1__ */ > > > +#endif /* __DISABLE_CRC32__ */ > > > > > > #endif /* _SMMINTRIN_H_INCLUDED */ > > > diff --git a/gcc/testsuite/gcc.target/i386/crc32-6.c b/gcc/testsuite/= gcc.target/i386/crc32-6.c > > > index 464e3444069..1f306534bb8 100644 > > > --- a/gcc/testsuite/gcc.target/i386/crc32-6.c > > > +++ b/gcc/testsuite/gcc.target/i386/crc32-6.c > > > @@ -7,7 +7,7 @@ > > > unsigned int > > > test_mm_crc32_u8 (unsigned int CRC, unsigned char V) > > > { > > > - return _mm_crc32_u8 (CRC, V); > > > + return __builtin_ia32_crc32qi (CRC, V); > > > > This test should not be changed, it correctly reports ISA mismatch. It > > even passes -mno-crc32. > > > > Uros. > > > > > } > > > > > > /* { dg-error "needs isa option -mcrc32" "" { target *-*-* } 0 } */ > > > diff --git a/gcc/testsuite/gcc.target/i386/crc32-7.c b/gcc/testsuite/= gcc.target/i386/crc32-7.c > > > new file mode 100644 > > > index 00000000000..2e310e38b82 > > > --- /dev/null > > > +++ b/gcc/testsuite/gcc.target/i386/crc32-7.c > > > @@ -0,0 +1,34 @@ > > > +/* { dg-do compile } */ > > > +/* { dg-options "-O2 -mcrc32" } */ > > > +/* { dg-final { scan-assembler "crc32b\[^\\n\]*eax" } } */ > > > +/* { dg-final { scan-assembler "crc32w\[^\\n\]*eax" } } */ > > > +/* { dg-final { scan-assembler "crc32l\[^\\n\]*eax" } } */ > > > +/* { dg-final { scan-assembler "crc32q\[^\\n\]*rax" { target { ! ia3= 2 } } } } */ > > > + > > > +#include > > > + > > > +unsigned int > > > +test_mm_crc32_u8 (unsigned int CRC, unsigned char V) > > > +{ > > > + return _mm_crc32_u8 (CRC, V); > > > +} > > > + > > > +unsigned int > > > +test_mm_crc32_u16 (unsigned int CRC, unsigned short V) > > > +{ > > > + return _mm_crc32_u16 (CRC, V); > > > +} > > > + > > > +unsigned int > > > +test_mm_crc32_u32 (unsigned int CRC, unsigned int V) > > > +{ > > > + return _mm_crc32_u32 (CRC, V); > > > +} > > > + > > > +#ifdef __x86_64__ > > > +unsigned long long > > > +test_mm_crc32_u64 (unsigned long long CRC, unsigned long long V) > > > +{ > > > + return _mm_crc32_u64 (CRC, V); > > > +} > > > +#endif > > > -- > > > 2.18.1 > > >