From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 70740 invoked by alias); 5 Jul 2019 15:43:34 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 70729 invoked by uid 89); 5 Jul 2019 15:43:33 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-4.5 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,GIT_PATCH_2,GIT_PATCH_3,KAM_ASCII_DIVIDERS,MEDICAL_SUBJECT,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.1 spammy=uros X-HELO: mail-io1-f46.google.com Received: from mail-io1-f46.google.com (HELO mail-io1-f46.google.com) (209.85.166.46) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 05 Jul 2019 15:43:31 +0000 Received: by mail-io1-f46.google.com with SMTP id f4so4494526ioh.6 for ; Fri, 05 Jul 2019 08:43:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to; bh=vYc2upns2SFGO2tQqXVgGYXhMJ+EzWDvinaASAxtcZQ=; b=nmfokoie9oWRccCPL6f/+a2BLVH2za0XFdiFDprhljLeqRUYpFjgFIVBKhzn7XdZME IUBq8DQCbPOR57v8AyGiMvSvL1GkXc2YFEIE0jrHhSrv+Gn+IVm/fFN9YMBQIV+o3fMR uY9cTvw0KkV2Oi3RoQw3ZXZSyG8JDaceMmwoE31VTt+Qy/yEMovOxPuA0khwbiRkdasf pG5GS2acI1jbZ5nd2fAQ4RC9upyhCiWFjFwZeE54f2dcaDv2FrnE8r4AzQFwrtbdXp9G UHR37v2mNroMdiJJgRsLBMaAtCyugRJQyr2q0P4cOFnds58AQjIMh0b20vvo0kTziG3i TpHA== MIME-Version: 1.0 References: In-Reply-To: From: Uros Bizjak Date: Fri, 05 Jul 2019 15:45:00 -0000 Message-ID: Subject: Re: [05/11] [i386] Fix ambiguous .md attribute uses To: "gcc-patches@gcc.gnu.org" , Jan Hubicka , Uros Bizjak , Richard Sandiford Content-Type: text/plain; charset="UTF-8" X-SW-Source: 2019-07/txt/msg00462.txt.bz2 On Fri, Jul 5, 2019 at 5:15 PM Richard Sandiford wrote: > > This patch is part of a series that fixes ambiguous attribute > uses in .md files, i.e. cases in which attributes didn't use > to specify an iterator, and in which could > have different values depending on the iterator chosen. > > No behavioural change except for dropping the unused *andnot3_bcst > permutations. > > > 2019-07-05 Richard Sandiford > > gcc/ > * config/i386/i386.md (*fop__3_i387) > (l2): Fix ambiguous uses > of .md attributes. > * config/i386/sse.md (*avx512pf_gatherpfsf_mask) > (*avx512pf_gatherpfdf_mask, *avx512pf_scatterpfsf_mask) > (*avx512pf_scatterpfdf_mask, *avx2_gathersi) > (*avx2_gathersi_2, *avx2_gatherdi) > (*avx2_gatherdi_2, *avx2_gatherdi_3): Likewise. > (*avx2_gatherdi_4, *avx512f_gathersi): Likewise. > (*avx512f_gathersi_2, *avx512f_gatherdi): Likewise. > (*avx512f_gatherdi_2, *avx512f_scattersi): Likewise. > (*avx512f_scatterdi): Likewise. > (*andnot3_bcst): Fix VI/VI48_AVX512VL typo. OK. Thanks, Uros. > Index: gcc/config/i386/i386.md > =================================================================== > --- gcc/config/i386/i386.md 2019-07-03 20:50:46.074319519 +0100 > +++ gcc/config/i386/i386.md 2019-07-05 15:05:55.216229452 +0100 > @@ -14755,7 +14755,7 @@ (define_insn "*fop__3_i38 > ] > (const_string "fop"))) > (set_attr "fp_int_src" "true") > - (set_attr "mode" "")]) > + (set_attr "mode" "")]) > > (define_insn "*fop_xf_4_i387" > [(set (match_operand:XF 0 "register_operand" "=f,f") > @@ -16457,7 +16457,7 @@ (define_expand "l { > rtx tmp = gen_reg_rtx (mode); > > - emit_insn (gen_sse4_1_round2 > + emit_insn (gen_sse4_1_round2 > (tmp, operands[1], GEN_INT (ROUND_ > | ROUND_NO_EXC))); > emit_insn (gen_fix_trunc2 > Index: gcc/config/i386/sse.md > =================================================================== > --- gcc/config/i386/sse.md 2019-07-03 20:50:46.078319486 +0100 > +++ gcc/config/i386/sse.md 2019-07-05 15:05:55.220229422 +0100 > @@ -12702,8 +12702,8 @@ (define_insn "*andnot3" > (const_string "")))]) > > (define_insn "*andnot3_bcst" > - [(set (match_operand:VI 0 "register_operand" "=v") > - (and:VI > + [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") > + (and:VI48_AVX512VL > (not:VI48_AVX512VL > (match_operand:VI48_AVX512VL 1 "register_operand" "v")) > (vec_duplicate:VI48_AVX512VL > @@ -18085,7 +18085,7 @@ (define_expand "avx512pf_gatherpfs > operands[3]), UNSPEC_VSIBADDR); > }) > > -(define_insn "*avx512pf_gatherpfsf_mask" > +(define_insn "*avx512pf_gatherpfsf_mask" > [(unspec > [(match_operand: 0 "register_operand" "Yk") > (match_operator: 5 "vsib_mem_operator" > @@ -18132,7 +18132,7 @@ (define_expand "avx512pf_gatherpfd > operands[3]), UNSPEC_VSIBADDR); > }) > > -(define_insn "*avx512pf_gatherpfdf_mask" > +(define_insn "*avx512pf_gatherpfdf_mask" > [(unspec > [(match_operand: 0 "register_operand" "Yk") > (match_operator:V8DF 5 "vsib_mem_operator" > @@ -18179,7 +18179,7 @@ (define_expand "avx512pf_scatterpf > operands[3]), UNSPEC_VSIBADDR); > }) > > -(define_insn "*avx512pf_scatterpfsf_mask" > +(define_insn "*avx512pf_scatterpfsf_mask" > [(unspec > [(match_operand: 0 "register_operand" "Yk") > (match_operator: 5 "vsib_mem_operator" > @@ -18228,7 +18228,7 @@ (define_expand "avx512pf_scatterpf > operands[3]), UNSPEC_VSIBADDR); > }) > > -(define_insn "*avx512pf_scatterpfdf_mask" > +(define_insn "*avx512pf_scatterpfdf_mask" > [(unspec > [(match_operand: 0 "register_operand" "Yk") > (match_operator:V8DF 5 "vsib_mem_operator" > @@ -21017,7 +21017,7 @@ (define_expand "avx2_gathersi" > operands[5]), UNSPEC_VSIBADDR); > }) > > -(define_insn "*avx2_gathersi" > +(define_insn "*avx2_gathersi" > [(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "=&x") > (unspec:VEC_GATHER_MODE > [(match_operand:VEC_GATHER_MODE 2 "register_operand" "0") > @@ -21037,7 +21037,7 @@ (define_insn "*avx2_gathersi" > (set_attr "prefix" "vex") > (set_attr "mode" "")]) > > -(define_insn "*avx2_gathersi_2" > +(define_insn "*avx2_gathersi_2" > [(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "=&x") > (unspec:VEC_GATHER_MODE > [(pc) > @@ -21078,7 +21078,7 @@ (define_expand "avx2_gatherdi" > operands[5]), UNSPEC_VSIBADDR); > }) > > -(define_insn "*avx2_gatherdi" > +(define_insn "*avx2_gatherdi" > [(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "=&x") > (unspec:VEC_GATHER_MODE > [(match_operand: 2 "register_operand" "0") > @@ -21098,7 +21098,7 @@ (define_insn "*avx2_gatherdi" > (set_attr "prefix" "vex") > (set_attr "mode" "")]) > > -(define_insn "*avx2_gatherdi_2" > +(define_insn "*avx2_gatherdi_2" > [(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "=&x") > (unspec:VEC_GATHER_MODE > [(pc) > @@ -21114,7 +21114,7 @@ (define_insn "*avx2_gatherdi_2" > (clobber (match_scratch:VEC_GATHER_MODE 1 "=&x"))] > "TARGET_AVX2" > { > - if (mode != mode) > + if (mode != mode) > return "%M2vgatherq\t{%4, %6, %x0|%x0, %6, %4}"; > return "%M2vgatherq\t{%4, %6, %0|%0, %6, %4}"; > } > @@ -21122,7 +21122,7 @@ (define_insn "*avx2_gatherdi_2" > (set_attr "prefix" "vex") > (set_attr "mode" "")]) > > -(define_insn "*avx2_gatherdi_3" > +(define_insn "*avx2_gatherdi_3" > [(set (match_operand: 0 "register_operand" "=&x") > (vec_select: > (unspec:VI4F_256 > @@ -21145,7 +21145,7 @@ (define_insn "*avx2_gatherdi_3" > (set_attr "prefix" "vex") > (set_attr "mode" "")]) > > -(define_insn "*avx2_gatherdi_4" > +(define_insn "*avx2_gatherdi_4" > [(set (match_operand: 0 "register_operand" "=&x") > (vec_select: > (unspec:VI4F_256 > @@ -21187,7 +21187,7 @@ (define_expand "_gathersi" > operands[5]), UNSPEC_VSIBADDR); > }) > > -(define_insn "*avx512f_gathersi" > +(define_insn "*avx512f_gathersi" > [(set (match_operand:VI48F 0 "register_operand" "=&v") > (unspec:VI48F > [(match_operand:VI48F 1 "register_operand" "0") > @@ -21208,7 +21208,7 @@ (define_insn "*avx512f_gathersi" > (set_attr "prefix" "evex") > (set_attr "mode" "")]) > > -(define_insn "*avx512f_gathersi_2" > +(define_insn "*avx512f_gathersi_2" > [(set (match_operand:VI48F 0 "register_operand" "=&v") > (unspec:VI48F > [(pc) > @@ -21249,7 +21249,7 @@ (define_expand "_gatherdi" > operands[5]), UNSPEC_VSIBADDR); > }) > > -(define_insn "*avx512f_gatherdi" > +(define_insn "*avx512f_gatherdi" > [(set (match_operand:VI48F 0 "register_operand" "=&v") > (unspec:VI48F > [(match_operand: 1 "register_operand" "0") > @@ -21270,7 +21270,7 @@ (define_insn "*avx512f_gatherdi" > (set_attr "prefix" "evex") > (set_attr "mode" "")]) > > -(define_insn "*avx512f_gatherdi_2" > +(define_insn "*avx512f_gatherdi_2" > [(set (match_operand:VI48F 0 "register_operand" "=&v") > (unspec:VI48F > [(pc) > @@ -21287,9 +21287,9 @@ (define_insn "*avx512f_gatherdi_2" > { > /* %X5 so that we don't emit any *WORD PTR for -masm=intel, as > gas changed what it requires incompatibly. */ > - if (mode != mode) > + if (mode != mode) > { > - if ( != 64) > + if ( != 64) > return "%M3vgatherq\t{%5, %x0%{%1%}|%x0%{%1%}, %X5}"; > else > return "%M3vgatherq\t{%5, %t0%{%1%}|%t0%{%1%}, %X5}"; > @@ -21318,7 +21318,7 @@ (define_expand "_scattersi > operands[4]), UNSPEC_VSIBADDR); > }) > > -(define_insn "*avx512f_scattersi" > +(define_insn "*avx512f_scattersi" > [(set (match_operator:VI48F 5 "vsib_mem_operator" > [(unspec:P > [(match_operand:P 0 "vsib_address_operand" "Tv") > @@ -21356,7 +21356,7 @@ (define_expand "_scatterdi > operands[4]), UNSPEC_VSIBADDR); > }) > > -(define_insn "*avx512f_scatterdi" > +(define_insn "*avx512f_scatterdi" > [(set (match_operator:VI48F 5 "vsib_mem_operator" > [(unspec:P > [(match_operand:P 0 "vsib_address_operand" "Tv")