* [PATCH, i386] Fix PR target/65671. Generate 32x4 extract even for DF in absence of AVX-512DQ.
@ 2015-04-09 14:37 Kirill Yukhin
2015-04-09 14:41 ` Jakub Jelinek
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Kirill Yukhin @ 2015-04-09 14:37 UTC (permalink / raw)
To: GCC Patches; +Cc: Uros Bizjak
Hello,
Patch in the bottom fixes PR target/65671.
It simply generates vextract32x4 (float form) for double extract.
Bootstrap & regtesting in progress.
I'll check it in if pass and back port to 4.9.x.
Feel free comment.
gcc/
* config/i386/sse.md: Generate vextract32x4 if AVX-512DQ
is disabled.
gcc/testsuite/
* gcc.target/i386/pr65671.c: New.
--
Thanks, K
commit cb8d5b1c3156d81ae81600217d0861be1aade0ec
Author: Kirill Yukhin <kirill.yukhin@intel.com>
Date: Thu Apr 9 13:05:54 2015 +0300
Fix PR target/65671. Generate 32x4 extract even for DF in absence of AVX-512DQ.
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 490fd6b..6d3b54a 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -7015,10 +7015,15 @@
(vec_select:<ssehalfvecmode>
(match_operand:VI8F_256 1 "register_operand" "v,v")
(parallel [(const_int 2) (const_int 3)])))]
- "TARGET_AVX"
+ "TARGET_AVX && <mask_avx512vl_condition> && <mask_avx512dq_condition>"
{
- if (TARGET_AVX512DQ && TARGET_AVX512VL)
- return "vextract<shuffletype>64x2\t{$0x1, %1, %0<mask_operand2>|%0<mask_operand2>, %1, 0x1}";
+ if (TARGET_AVX512VL)
+ {
+ if (TARGET_AVX512DQ)
+ return "vextract<shuffletype>64x2\t{$0x1, %1, %0<mask_operand2>|%0<mask_operand2>, %1, 0x1}";
+ else
+ return "vextract<shuffletype>32x4\t{$0x1, %1, %0|%0, %1, 0x1}";
+ }
else
return "vextract<i128>\t{$0x1, %1, %0|%0, %1, 0x1}";
}
diff --git a/gcc/testsuite/gcc.target/i386/pr65671.c b/gcc/testsuite/gcc.target/i386/pr65671.c
new file mode 100644
index 0000000..8e5d00d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr65671.c
@@ -0,0 +1,15 @@
+/* PR target/65671 */
+/* { dg-do assemble } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -mavx512vl -ffixed-ymm16" } */
+
+#include <x86intrin.h>
+
+register __m256d a asm ("ymm16");
+__m128d b;
+
+void
+foo ()
+{
+ b = _mm256_extractf128_pd (a, 1);
+}
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH, i386] Fix PR target/65671. Generate 32x4 extract even for DF in absence of AVX-512DQ.
2015-04-09 14:37 [PATCH, i386] Fix PR target/65671. Generate 32x4 extract even for DF in absence of AVX-512DQ Kirill Yukhin
@ 2015-04-09 14:41 ` Jakub Jelinek
2015-04-09 14:56 ` Kirill Yukhin
2015-04-09 15:50 ` Uros Bizjak
2015-04-11 13:58 ` Jakub Jelinek
2 siblings, 1 reply; 5+ messages in thread
From: Jakub Jelinek @ 2015-04-09 14:41 UTC (permalink / raw)
To: Kirill Yukhin; +Cc: GCC Patches, Uros Bizjak
On Thu, Apr 09, 2015 at 06:37:01PM +0400, Kirill Yukhin wrote:
> gcc/
> * config/i386/sse.md: Generate vextract32x4 if AVX-512DQ
Please use
PR target/65671
* config/i386/sse.md (vec_extract_hi_<mode><mask_name>): ...
(both PR line and name of pattern missing).
Jakub
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH, i386] Fix PR target/65671. Generate 32x4 extract even for DF in absence of AVX-512DQ.
2015-04-09 14:37 [PATCH, i386] Fix PR target/65671. Generate 32x4 extract even for DF in absence of AVX-512DQ Kirill Yukhin
2015-04-09 14:41 ` Jakub Jelinek
@ 2015-04-09 15:50 ` Uros Bizjak
2015-04-11 13:58 ` Jakub Jelinek
2 siblings, 0 replies; 5+ messages in thread
From: Uros Bizjak @ 2015-04-09 15:50 UTC (permalink / raw)
To: Kirill Yukhin; +Cc: GCC Patches
On Thu, Apr 9, 2015 at 4:37 PM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:
> Patch in the bottom fixes PR target/65671.
>
> It simply generates vextract32x4 (float form) for double extract.
>
> Bootstrap & regtesting in progress.
>
> I'll check it in if pass and back port to 4.9.x.
> Feel free comment.
>
> gcc/
> * config/i386/sse.md: Generate vextract32x4 if AVX-512DQ
> is disabled.
>
> gcc/testsuite/
> * gcc.target/i386/pr65671.c: New.
>
OK with fixed ChangeLogs. (Please add PR target/65671 to both ChangeLogs).
Thanks,
Uros.
> commit cb8d5b1c3156d81ae81600217d0861be1aade0ec
> Author: Kirill Yukhin <kirill.yukhin@intel.com>
> Date: Thu Apr 9 13:05:54 2015 +0300
>
> Fix PR target/65671. Generate 32x4 extract even for DF in absence of AVX-512DQ.
>
> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> index 490fd6b..6d3b54a 100644
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -7015,10 +7015,15 @@
> (vec_select:<ssehalfvecmode>
> (match_operand:VI8F_256 1 "register_operand" "v,v")
> (parallel [(const_int 2) (const_int 3)])))]
> - "TARGET_AVX"
> + "TARGET_AVX && <mask_avx512vl_condition> && <mask_avx512dq_condition>"
> {
> - if (TARGET_AVX512DQ && TARGET_AVX512VL)
> - return "vextract<shuffletype>64x2\t{$0x1, %1, %0<mask_operand2>|%0<mask_operand2>, %1, 0x1}";
> + if (TARGET_AVX512VL)
> + {
> + if (TARGET_AVX512DQ)
> + return "vextract<shuffletype>64x2\t{$0x1, %1, %0<mask_operand2>|%0<mask_operand2>, %1, 0x1}";
> + else
> + return "vextract<shuffletype>32x4\t{$0x1, %1, %0|%0, %1, 0x1}";
> + }
> else
> return "vextract<i128>\t{$0x1, %1, %0|%0, %1, 0x1}";
> }
> diff --git a/gcc/testsuite/gcc.target/i386/pr65671.c b/gcc/testsuite/gcc.target/i386/pr65671.c
> new file mode 100644
> index 0000000..8e5d00d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr65671.c
> @@ -0,0 +1,15 @@
> +/* PR target/65671 */
> +/* { dg-do assemble } */
> +/* { dg-require-effective-target lp64 } */
> +/* { dg-options "-O2 -mavx512vl -ffixed-ymm16" } */
> +
> +#include <x86intrin.h>
> +
> +register __m256d a asm ("ymm16");
> +__m128d b;
> +
> +void
> +foo ()
> +{
> + b = _mm256_extractf128_pd (a, 1);
> +}
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH, i386] Fix PR target/65671. Generate 32x4 extract even for DF in absence of AVX-512DQ.
2015-04-09 14:37 [PATCH, i386] Fix PR target/65671. Generate 32x4 extract even for DF in absence of AVX-512DQ Kirill Yukhin
2015-04-09 14:41 ` Jakub Jelinek
2015-04-09 15:50 ` Uros Bizjak
@ 2015-04-11 13:58 ` Jakub Jelinek
2 siblings, 0 replies; 5+ messages in thread
From: Jakub Jelinek @ 2015-04-11 13:58 UTC (permalink / raw)
To: Kirill Yukhin; +Cc: GCC Patches, Uros Bizjak
On Thu, Apr 09, 2015 at 06:37:01PM +0400, Kirill Yukhin wrote:
> gcc/
> * config/i386/sse.md: Generate vextract32x4 if AVX-512DQ
> is disabled.
>
> gcc/testsuite/
> * gcc.target/i386/pr65671.c: New.
The testcase fails if gas doesn't have AVX512VL support (my only has
AVX512F).
Fixed thusly, committed as obvious.
2015-04-11 Jakub Jelinek <jakub@redhat.com>
PR target/65671
* gcc.target/i386/pr65671.c: Require avx512vl effective target.
--- gcc/testsuite/gcc.target/i386/pr65671.c.jj 2015-04-11 10:44:30.579838982 +0200
+++ gcc/testsuite/gcc.target/i386/pr65671.c 2015-04-11 15:52:19.778368299 +0200
@@ -1,6 +1,7 @@
/* PR target/65671 */
/* { dg-do assemble } */
/* { dg-require-effective-target lp64 } */
+/* { dg-require-effective-target avx512vl } */
/* { dg-options "-O2 -mavx512vl -ffixed-ymm16" } */
#include <x86intrin.h>
Jakub
^ permalink raw reply [flat|nested] 5+ messages in thread
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2015-04-09 14:37 [PATCH, i386] Fix PR target/65671. Generate 32x4 extract even for DF in absence of AVX-512DQ Kirill Yukhin
2015-04-09 14:41 ` Jakub Jelinek
2015-04-09 14:56 ` Kirill Yukhin
2015-04-09 15:50 ` Uros Bizjak
2015-04-11 13:58 ` Jakub Jelinek
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