From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by sourceware.org (Postfix) with ESMTPS id 693B13858C2B for ; Thu, 20 Jul 2023 06:49:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 693B13858C2B Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-lf1-x135.google.com with SMTP id 2adb3069b0e04-4fdd14c1fbfso665140e87.1 for ; Wed, 19 Jul 2023 23:49:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1689835795; x=1690440595; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=m4bS+iogW6+937xTIdxIctn2MuVo2SFuhyQZp0Q2dZ8=; b=HWe2CLGaKNPmj5TsqlqpDRM5UgrjmJa/Evr8vJ75uOl012MXMLCaBS/nPz82yzXfwY 9dae2mDzu6MkndIpfdgmOwVM35HiECmRTHDCjaBTsLmdnoJtSpJ/gGzrS71aqOfYLfyy sQ3LTNrfhApo83nrU+msGwOpNM1W8IHaO4y9/WZZ/u6cOjnGaCnjji3L1jnxqqs0xUB1 9dwZBB3NAhtKXM7RPLlqEuOe5rG0G4q+sHwLWAjHKjoQdXLfzgKjAxnJAyLRqH4bc5ck R+vCAjgLMmvQ8xpDOOHKwwxoaHM1DJrjBrNXYrsyn2iVWrKNpMK9BEMDFjNUEgQMaIej D86g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689835795; x=1690440595; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=m4bS+iogW6+937xTIdxIctn2MuVo2SFuhyQZp0Q2dZ8=; b=iIYRu+Qe/fzn5VHztSkXu3D+hrr9JYyzaShErI1zLCU2a2gwaJxBKFVBrSSCmf/FyG Wny4K2xicTw/CK3C3upjLXS48pQzWJWVvxbt6b0JxDIrHYModMNpFArN2QQUm3tb6ga6 EbhhxbmEz3qonh/+DJSyAFlsuMDHSGEsZiTFHH0emJ6PHIzn5XdlIzsSCG9Dmz3LJ88i XNmudgB0s8xpqGOCYZNgezATxUQh/nPe17vTqFxoLgKonryboDvBwbltRRsyHsT1fpUl 9A0l0pe76gfnHkMhC1N57TntscVNFL7uTkRKODujxu0t/ClnWpmVxGjx4NWubqGlBm97 HLLg== X-Gm-Message-State: ABy/qLbx7F2mUIQuqkyn4MDvRM8UGrSv6c5ruMxktGIIE6r+hJuvP0id gHBUscJSIdBMNxWf5n7ZkO8BUZZiUkBQdYlo9g5zJCgOoXPLYA== X-Google-Smtp-Source: APBJJlHwzg7M/68GsXCKD07KiR+kxWoaz6dcsvtDqkheMb4PTjPvYyOrQ0duDUffXzt91aQyVRGUbOrgOpN0gzvFepE= X-Received: by 2002:a19:645d:0:b0:4f8:6bca:50d7 with SMTP id b29-20020a19645d000000b004f86bca50d7mr1318597lfj.13.1689835794644; Wed, 19 Jul 2023 23:49:54 -0700 (PDT) MIME-Version: 1.0 References: <009201d9ba7c$a64374d0$f2ca5e70$@nextmovesoftware.com> In-Reply-To: <009201d9ba7c$a64374d0$f2ca5e70$@nextmovesoftware.com> From: Uros Bizjak Date: Thu, 20 Jul 2023 08:49:43 +0200 Message-ID: Subject: Re: [x86_64 PATCH] More TImode parameter passing improvements. To: Roger Sayle Cc: gcc-patches@gcc.gnu.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, Jul 19, 2023 at 10:07=E2=80=AFPM Roger Sayle wrote: > > > This patch is the next piece of a solution to the x86_64 ABI issues in > PR 88873. This splits the *concat3_3 define_insn_and_split > into two patterns, a TARGET_64BIT *concatditi3_3 and a !TARGET_64BIT > *concatsidi3_3. This allows us to add an additional alternative to the > the 64-bit version, enabling the register allocator to perform this > operation using SSE registers, which is implemented/split after reload > using vec_concatv2di. > > To demonstrate the improvement, the test case from PR88873: > > typedef struct { double x, y; } s_t; > > s_t foo (s_t a, s_t b, s_t c) > { > return (s_t){ __builtin_fma(a.x, b.x, c.x), __builtin_fma (a.y, b.y, c.= y) > }; > } > > when compiled with -O2 -march=3Dcascadelake, currently generates: > > foo: vmovq %xmm2, -56(%rsp) > movq -56(%rsp), %rax > vmovq %xmm3, -48(%rsp) > vmovq %xmm4, -40(%rsp) > movq -48(%rsp), %rcx > vmovq %xmm5, -32(%rsp) > vmovq %rax, %xmm6 > movq -40(%rsp), %rax > movq -32(%rsp), %rsi > vpinsrq $1, %rcx, %xmm6, %xmm6 > vmovq %xmm0, -24(%rsp) > vmovq %rax, %xmm7 > vmovq %xmm1, -16(%rsp) > vmovapd %xmm6, %xmm2 > vpinsrq $1, %rsi, %xmm7, %xmm7 > vfmadd132pd -24(%rsp), %xmm7, %xmm2 > vmovapd %xmm2, -56(%rsp) > vmovsd -48(%rsp), %xmm1 > vmovsd -56(%rsp), %xmm0 > ret > > with this change, we avoid many of the reloads via memory, > > foo: vpunpcklqdq %xmm3, %xmm2, %xmm7 > vpunpcklqdq %xmm1, %xmm0, %xmm6 > vpunpcklqdq %xmm5, %xmm4, %xmm2 > vmovdqa %xmm7, -24(%rsp) > vmovdqa %xmm6, %xmm1 > movq -16(%rsp), %rax > vpinsrq $1, %rax, %xmm7, %xmm4 > vmovapd %xmm4, %xmm6 > vfmadd132pd %xmm1, %xmm2, %xmm6 > vmovapd %xmm6, -24(%rsp) > vmovsd -16(%rsp), %xmm1 > vmovsd -24(%rsp), %xmm0 > ret > > > This patch has been tested on x86_64-pc-linux-gnu with make bootstrap > and make -k check, both with and without --target_board=3Dunix{-m32} > with no new failures. Ok for mainline? > > > 2023-07-19 Roger Sayle > > gcc/ChangeLog > * config/i386/i386-expand.cc (ix86_expand_move): Don't call > force_reg, to use SUBREG rather than create a new pseudo when > inserting DFmode fields into TImode with insvti_{high,low}part. > (*concat3_3): Split into two define_insn_and_split... > (*concatditi3_3): 64-bit implementation. Provide alternative > that allows register allocation to use SSE registers that is > split into vec_concatv2di after reload. > (*concatsidi3_3): 32-bit implementation. > > gcc/testsuite/ChangeLog > * gcc.target/i386/pr88873.c: New test case. diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.c= c index f9b0dc6..9c3febe 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -558,7 +558,7 @@ ix86_expand_move (machine_mode mode, rtx operands[]) op0 =3D SUBREG_REG (op0); tmp =3D gen_rtx_AND (TImode, copy_rtx (op0), tmp); if (mode =3D=3D DFmode) - op1 =3D force_reg (DImode, gen_lowpart (DImode, op1)); + op1 =3D gen_lowpart (DImode, op1); Please note that gen_lowpart will ICE when op1 is a SUBREG. This is the reason that we need to first force a SUBREG to a register and then perform gen_lowpart, and it is necessary to avoid ICE. op1 =3D gen_rtx_ZERO_EXTEND (TImode, op1); op1 =3D gen_rtx_IOR (TImode, tmp, op1); } @@ -570,7 +570,7 @@ ix86_expand_move (machine_mode mode, rtx operands[]) op0 =3D SUBREG_REG (op0); tmp =3D gen_rtx_AND (TImode, copy_rtx (op0), tmp); if (mode =3D=3D DFmode) - op1 =3D force_reg (DImode, gen_lowpart (DImode, op1)); + op1 =3D gen_lowpart (DImode, op1); Also here. op1 =3D gen_rtx_ZERO_EXTEND (TImode, op1); op1 =3D gen_rtx_ASHIFT (TImode, op1, GEN_INT (64)); op1 =3D gen_rtx_IOR (TImode, tmp, op1); Uros.