From: Uros Bizjak <ubizjak@gmail.com>
To: Hongtao Liu <crazylht@gmail.com>
Cc: GCC Patches <gcc-patches@gcc.gnu.org>,
Kirill Yukhin <kirill.yukhin@gmail.com>,
"H. J. Lu" <hjl.tools@gmail.com>
Subject: Re: [PATCH 1/4][PR target/88808]Enable bitwise operator for AVX512 masks.
Date: Mon, 17 Aug 2020 11:20:14 +0200 [thread overview]
Message-ID: <CAFULd4btgcasuzk_jLBmiC=s2JMYusvyxbiEgtMJ6jg_LnbXEw@mail.gmail.com> (raw)
In-Reply-To: <CAMZc-bwPxPVLCDeAZWxFzx2=ZWUSPrAVYiAGDRgPx5YviZJ35A@mail.gmail.com>
On Fri, Aug 14, 2020 at 10:22 AM Hongtao Liu <crazylht@gmail.com> wrote:
>
> Hi:
> First, since avx512 masks involve both vector isa and general part,
> so i add both maintainers to the maillist.
>
> I'm doing this in 4 steps:
> 1 - Add cost model for operation of mask registers.
> 2 - Introduce new cover class INT_MASK_REGS, this will enable direct
> move between gpr and mask registers in pass_reload by consideration of
> cost model, this is similar as INT_SSE_REGS.
> 3 - Tune cost model.
> 4 - Enable operator or/xor/and/andn/not for mask register. kxnor is
> not enabled since there's no corresponding instruction for general
> registers, 64bit mask op is not enabled for 32bit target.
> kadd/kshift/ktest are not merged into general versionsadd/ashl/test
> since i think it would be odd to use mask register for those
> operations.
>
> Bootstrap is ok, regression test is ok for i386/x86-64 result.
> There's some improvement for performance of SPEC2017 tested on SKL,
> i observe there're many spills from integer to mask registers instead
> of memory which is the reason for the improvement.
+ if (MASK_CLASS_P (regclass))
+ {
+ int index;
+ switch (GET_MODE_SIZE (mode))
+ {
+ case 1:
+ index = 0;
+ break;
+ case 2:
+ index = 1;
+ break;
+ default:
+ index = 3;
Max index = 2!
+ break;
+ }
+
+ if (in == 2)
+ return MAX (ix86_cost->hard_register.mask_load[index],
+ ix86_cost->hard_register.mask_store[index]);
+ return in ? ix86_cost->hard_register.mask_load[2]
+ : ix86_cost->hard_register.mask_store[2];
+ }
Are DImode loads and stores assumed to cost the same as SImode? A
comment would be nice here.
Uros.
next prev parent reply other threads:[~2020-08-17 9:20 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-14 8:23 Hongtao Liu
2020-08-17 9:20 ` Uros Bizjak [this message]
2020-08-19 1:53 ` Hongtao Liu
2020-08-19 6:29 ` Uros Bizjak
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAFULd4btgcasuzk_jLBmiC=s2JMYusvyxbiEgtMJ6jg_LnbXEw@mail.gmail.com' \
--to=ubizjak@gmail.com \
--cc=crazylht@gmail.com \
--cc=gcc-patches@gcc.gnu.org \
--cc=hjl.tools@gmail.com \
--cc=kirill.yukhin@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).