From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw1-x112c.google.com (mail-yw1-x112c.google.com [IPv6:2607:f8b0:4864:20::112c]) by sourceware.org (Postfix) with ESMTPS id A885A3858D28 for ; Fri, 2 Dec 2022 09:55:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org A885A3858D28 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-yw1-x112c.google.com with SMTP id 00721157ae682-3c21d6e2f3aso43370667b3.10 for ; Fri, 02 Dec 2022 01:55:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=P81agM75b0FNfStGAB+y1t2LLVRI2PhbEWwBPQ1vJaA=; b=ceIPWJ/ObNWEdYpPyF12KhkicDEMR8J+p0NtG76ol3uMQqzjbhyb70FLeGo7Qqy6yx OZCJrUYUxl9xbelYG0WecDK9w8O4w5RIY/X/vRe59z/8XVzre5ygfnJt5jwpEWuSkZSs l6b2WoyOhmO2/RLFm5swzIIJP0hJ6XJk2cfFpEjrkFnC+HyLuPOx0wBGEvTajkOLkjoG Wy7s5knCaLHVT0CEEUk0qrKyikPmEfOpVEXtCkk+yegFvc4FC2EiNc0omjmObK5/NZZd GMRe63twh8FlUO5Rt1b02YClzKVg4Z6d0fi+/CM5MuTAILBrK3SjcvVW3z7jp/5rQPZZ W3DQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=P81agM75b0FNfStGAB+y1t2LLVRI2PhbEWwBPQ1vJaA=; b=Tcu5rPChETBoOlkUFEZzbHnzsrMCKJtfKqQ7jFIfUz9WrZLvIY9mXYKsHwyAUshDio +osUCLpX4KZ4RGHzdXBBJQ3KMGsRh9NzKtPLLBCYmIIH8CfPvYHsQt7/TPVW01swWG9w byLpCeFuNWc7gftqsfaeIYM61GyWkv8yQrhpwRVxbwJxk1IjjZ2Nm21p3arIpSDmCZRt 26E4jb/eCUR6q0FuY3VICcjuAIi5dIjsMT3cnIbmWGg7RwHgqWtfMhVUPLLHF6TG4Rz7 QUVEJ506vGD4gN8QXh3W1v2a25tN7O5cpDSANGAdUS48Z+4Jtx0LCb7gvnvtjyUzqyL7 dh2g== X-Gm-Message-State: ANoB5pnGYeHq2r71gQ2afVNWLCfTVeXjlbrPKbusVXGRBPV1gIOVdJJQ KrZgxXjAAe7Hhwje6dM7vejjuTIWM3vzMzoDZpsNgfRQn5A= X-Google-Smtp-Source: AA0mqf6womWRa38+YavfE17kJ8sR/s5CgjBm9Neq6Ppk2GsHr7QFY6D8o+zqKhASM0xRMzEN5rXmG4BRwgYeoCrG9to= X-Received: by 2002:a81:8684:0:b0:360:7f0a:1620 with SMTP id w126-20020a818684000000b003607f0a1620mr47399475ywf.192.1669974901940; Fri, 02 Dec 2022 01:55:01 -0800 (PST) MIME-Version: 1.0 References: <57fb7194-0c9a-2b7c-d671-521b9b4d2b71@suse.cz> In-Reply-To: <57fb7194-0c9a-2b7c-d671-521b9b4d2b71@suse.cz> From: Uros Bizjak Date: Fri, 2 Dec 2022 10:54:51 +0100 Message-ID: Subject: Re: [PATCH] i386: fix assert (__builtin_cpu_supports ("x86-64") >= 0) To: =?UTF-8?Q?Martin_Li=C5=A1ka?= Cc: gcc-patches@gcc.gnu.org, Jakub Jelinek , Jan Hubicka Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Fri, Dec 2, 2022 at 10:46 AM Martin Li=C5=A1ka wrote: > > PING^1 > > On 11/25/22 13:57, Martin Li=C5=A1ka wrote: > > Similar story as PR103661, we again return a negative number > > for __builtin_cpu_supports: > > > > Documentation says: > > > > int __builtin_cpu_supports(const char *feature) > > This function returns a positive integer if the run-time CPU supports f= eature and returns 0 otherwise. > > while we return -2147483648. > > > > Moreover, I noticed "x86-64" is not a valid option for __builtin_cpu_is= , > > but for __builtin_cpu_supports. > > > > Patch can bootstrap on x86_64-linux-gnu and survives regression tests. > > > > Ready to be installed? > > Thanks, > > Martin > > > > PR target/107551 > > > > gcc/ChangeLog: > > > > * config/i386/i386-builtins.cc (fold_builtin_cpu): Use same path > > as for PR103661. > > * doc/extend.texi: Fix "x86-64" use. > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/i386/builtin_target.c: Add more checks. I'm not quite familiar with this part of the compiler, but if Jakub is OK with the patch, consider it rubber-stamped OK. Thanks, Uros. > > --- > > gcc/config/i386/i386-builtins.cc | 25 ++++++++----------- > > gcc/doc/extend.texi | 22 ++++++++-------- > > .../gcc.target/i386/builtin_target.c | 5 ++++ > > 3 files changed, 26 insertions(+), 26 deletions(-) > > > > diff --git a/gcc/config/i386/i386-builtins.cc b/gcc/config/i386/i386-bu= iltins.cc > > index eacdf072244..c57c1380298 100644 > > --- a/gcc/config/i386/i386-builtins.cc > > +++ b/gcc/config/i386/i386-builtins.cc > > @@ -2181,18 +2181,14 @@ fold_builtin_cpu (tree fndecl, tree *args) > > varpool_node::add (ix86_cpu_features2_var); > > } > > > > + /* Skip __cpu_features[0]. */ > > feature -=3D INT_TYPE_SIZE; > > - field_val =3D 1U << (feature % INT_TYPE_SIZE); > > tree index =3D size_int (feature / INT_TYPE_SIZE); > > + feature =3D feature % INT_TYPE_SIZE; > > array_elt =3D build4 (ARRAY_REF, unsigned_type_node, > > ix86_cpu_features2_var, > > index, NULL_TREE, NULL_TREE); > > /* Return __cpu_features2[index] & field_val */ > > - final =3D build2 (BIT_AND_EXPR, unsigned_type_node, > > - array_elt, > > - build_int_cstu (unsigned_type_node, > > - field_val)); > > - return build1 (NOP_EXPR, integer_type_node, final); > > } > > else > > { > > @@ -2209,16 +2205,17 @@ fold_builtin_cpu (tree fndecl, tree *args) > > array_elt =3D build4 (ARRAY_REF, unsigned_type_node, ref, > > integer_zero_node, NULL_TREE, NULL_TREE); > > > > - field_val =3D (1U << feature); > > /* Return __cpu_model.__cpu_features[0] & field_val */ > > - final =3D build2 (BIT_AND_EXPR, unsigned_type_node, array_elt, > > - build_int_cstu (unsigned_type_node, field_val))= ; > > - if (feature =3D=3D (INT_TYPE_SIZE - 1)) > > - return build2 (NE_EXPR, integer_type_node, final, > > - build_int_cst (unsigned_type_node, 0)); > > - else > > - return build1 (NOP_EXPR, integer_type_node, final); > > } > > + > > + field_val =3D (1U << feature); > > + final =3D build2 (BIT_AND_EXPR, unsigned_type_node, array_elt, > > + build_int_cstu (unsigned_type_node, field_val)); > > + if (feature =3D=3D (INT_TYPE_SIZE - 1)) > > + return build2 (NE_EXPR, integer_type_node, final, > > + build_int_cst (unsigned_type_node, 0)); > > + else > > + return build1 (NOP_EXPR, integer_type_node, final); > > } > > gcc_unreachable (); > > } > > diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi > > index b1dd39e64b8..d3812fa55b0 100644 > > --- a/gcc/doc/extend.texi > > +++ b/gcc/doc/extend.texi > > @@ -21897,18 +21897,6 @@ AMD Family 19h Zen version 3. > > > > @item znver4 > > AMD Family 19h Zen version 4. > > - > > -@item x86-64 > > -Baseline x86-64 microarchitecture level (as defined in x86-64 psABI). > > - > > -@item x86-64-v2 > > -x86-64-v2 microarchitecture level. > > - > > -@item x86-64-v3 > > -x86-64-v3 microarchitecture level. > > - > > -@item x86-64-v4 > > -x86-64-v4 microarchitecture level. > > @end table > > > > Here is an example: > > @@ -22002,6 +21990,16 @@ VPCLMULQDQ instructions. > > AVX512VNNI instructions. > > @item avx512bitalg > > AVX512BITALG instructions. > > +@item x86-64 > > +Baseline x86-64 microarchitecture level (as defined in x86-64 psABI). > > +@item x86-64-v2 > > +x86-64-v2 microarchitecture level. > > +@item x86-64-v3 > > +x86-64-v3 microarchitecture level. > > +@item x86-64-v4 > > +x86-64-v4 microarchitecture level. > > + > > + > > @end table > > > > Here is an example: > > diff --git a/gcc/testsuite/gcc.target/i386/builtin_target.c b/gcc/tests= uite/gcc.target/i386/builtin_target.c > > index 3e7505a8c3a..fff643c13b0 100644 > > --- a/gcc/testsuite/gcc.target/i386/builtin_target.c > > +++ b/gcc/testsuite/gcc.target/i386/builtin_target.c > > @@ -95,6 +95,11 @@ quick_check () > > > > assert (__builtin_cpu_supports ("avx512vpopcntdq") >=3D 0); > > > > + assert (__builtin_cpu_supports ("x86-64") >=3D 0); > > + assert (__builtin_cpu_supports ("x86-64-v2") >=3D 0); > > + assert (__builtin_cpu_supports ("x86-64-v3") >=3D 0); > > + assert (__builtin_cpu_supports ("x86-64-v4") >=3D 0); > > + > > /* Check CPU type. */ > > assert (__builtin_cpu_is ("amd") >=3D 0); > > >