From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qk1-x736.google.com (mail-qk1-x736.google.com [IPv6:2607:f8b0:4864:20::736]) by sourceware.org (Postfix) with ESMTPS id 904803858416 for ; Tue, 6 Jun 2023 09:08:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 904803858416 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-qk1-x736.google.com with SMTP id af79cd13be357-75ca95c4272so532315185a.0 for ; Tue, 06 Jun 2023 02:08:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686042535; x=1688634535; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=WGJtuqccB/19kgCo/ftjYJluncRLK+sYrz5Fm4aPDqY=; b=PTDnuiKAEnqKxZBaI5//nlaRLw4MrhhpzTcyRnXXsdrSDG6RIvrsKcXxPkjrAD+JbK z0z8ysXmshdltJwhWZlNrKNXL/jHWKlZQoX9pvplKSoVUSsMvTqJMo6bdS3gNV3JWmcQ zi0sTBIGSefCsc0N1psb/+suhQOEq+u/tOhrHUyReABi3WkNwf+ACzD58HYH8kj3znpO rIZnCRKO7ssARB+qG4G4YDKBjZD6sppT6LXRrbZeGlpj4TXYudAWOra5Qmj2jF3SZO5d yKBzuqoA0znItqK2f/q/Agxril2XYBwcc6shkTdZSYjWaMcNULsUPoZ6TMoMjpg2GzTw XL+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686042535; x=1688634535; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WGJtuqccB/19kgCo/ftjYJluncRLK+sYrz5Fm4aPDqY=; b=La/YNTLdN3JrfqnKiSQm1K4vI4snRWg4AQr5rhDOxk8XWaNU0i3YI7GRnYT8tntU+A /2TSIDe0/5ZNuRaVqwE/lew3Rf85PA6iYUAwHJXQZEVm8ZCwD1NJJAA2mH0b69HWYv+C E789iwO/PqO+H3ojCwE7M5kAWezMGoWcgdZvHiOAR82Ecm8PUY4NQ638GI9hqdygZz4t pm1tviwpc4RhAj3mK4SRk74c0etWoUEcsPCTAQTt7re0nFH5D6FpfWgLkvDUbBMp6XeC 0M7x6mepxHj1XTjw5ws5ElzHqrg8BNqtOcoxGPsOjoR23YnH8VVn8rBA2CwHkMcsnULC IUpA== X-Gm-Message-State: AC+VfDzmYQyUtPrtyFZS6ObgGpBN342OZme6dVFnNLTZyS7Y1yZfpAzt wJfv0p1EiRvmMTTt9zNn+y2F0aXHw905nFxz638= X-Google-Smtp-Source: ACHHUZ7LpGtMKvelCHWNIffQdyr//FzbZoPJxcwsjGAOxpwGUYR53OWA2Shi8OoGU0vf4FT0Ac/dlAoO54YO+OoTmp0= X-Received: by 2002:a05:6214:268e:b0:62b:58af:9a00 with SMTP id gm14-20020a056214268e00b0062b58af9a00mr1559645qvb.44.1686042534827; Tue, 06 Jun 2023 02:08:54 -0700 (PDT) MIME-Version: 1.0 References: <20230606043121.24843-1-hongtao.liu@intel.com> In-Reply-To: <20230606043121.24843-1-hongtao.liu@intel.com> From: Uros Bizjak Date: Tue, 6 Jun 2023 11:08:43 +0200 Message-ID: Subject: Re: [PATCH] Fold _mm{, 256, 512}_abs_{epi8, epi16, epi32, epi64} into gimple ABSU_EXPR + VCE. To: liuhongt Cc: gcc-patches@gcc.gnu.org, crazylht@gmail.com, hjl.tools@gmail.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Tue, Jun 6, 2023 at 6:33=E2=80=AFAM liuhongt via Gcc-patches wrote: > > r14-1145 fold the intrinsics into gimple ABS_EXPR which has UB for > TYPE_MIN, but PABSB will store unsigned result into dst. The patch > uses ABSU_EXPR + VCE instead of ABS_EXPR. > > Also don't fold _mm_abs_{pi8,pi16,pi32} w/o TARGET_64BIT since 64-bit > vector absm2 is guarded with TARGET_MMX_WITH_SSE. > > Bootstrapped and regtested on x86_64-linux-gnu{-m32,}. > Ok for trunk? > > > gcc/ChangeLog: > > PR target/110108 > * config/i386/i386.cc (ix86_gimple_fold_builtin): Fold > _mm{,256,512}_abs_{epi8,epi16,epi32,epi64} into gimple > ABSU_EXPR + VCE, don't fold _mm_abs_{pi8,pi16,pi32} w/o > TARGET_64BIT. > * config/i386/i386-builtin.def: Replace CODE_FOR_nothing with > real codename for __builtin_ia32_pabs{b,w,d}. > > gcc/testsuite/ChangeLog: > > * gcc.target/i386/pr110108.c: New test. > --- > gcc/config/i386/i386-builtin.def | 6 ++-- > gcc/config/i386/i386.cc | 44 ++++++++++++++++++++---- > gcc/testsuite/gcc.target/i386/pr110108.c | 16 +++++++++ > 3 files changed, 56 insertions(+), 10 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/i386/pr110108.c > > diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-buil= tin.def > index 383b68a9bb8..7ba5b6a9d11 100644 > --- a/gcc/config/i386/i386-builtin.def > +++ b/gcc/config/i386/i386-builtin.def > @@ -900,11 +900,11 @@ BDESC (OPTION_MASK_ISA_SSE3, 0, CODE_FOR_sse3_hsubv= 2df3, "__builtin_ia32_hsubpd" > > /* SSSE3 */ > BDESC (OPTION_MASK_ISA_SSSE3, 0, CODE_FOR_nothing, "__builtin_ia32_pabsb= 128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI) > -BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing,= "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI= ) > +BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_ssse3_ab= sv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTY= PE_V8QI) > BDESC (OPTION_MASK_ISA_SSSE3, 0, CODE_FOR_nothing, "__builtin_ia32_pabsw= 128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI) > -BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing,= "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI= ) > +BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_ssse3_ab= sv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTY= PE_V4HI) > BDESC (OPTION_MASK_ISA_SSSE3, 0, CODE_FOR_nothing, "__builtin_ia32_pabsd= 128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI) > -BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing,= "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI= ) > +BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_ssse3_ab= sv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTY= PE_V2SI) > > BDESC (OPTION_MASK_ISA_SSSE3, 0, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_= ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8H= I) > BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_ssse3_ph= addwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4H= I_FTYPE_V4HI_V4HI) > diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc > index d4ff56ee8dd..b09b3c79e99 100644 > --- a/gcc/config/i386/i386.cc > +++ b/gcc/config/i386/i386.cc > @@ -18433,6 +18433,7 @@ bool > ix86_gimple_fold_builtin (gimple_stmt_iterator *gsi) > { > gimple *stmt =3D gsi_stmt (*gsi), *g; > + gimple_seq stmts =3D NULL; > tree fndecl =3D gimple_call_fndecl (stmt); > gcc_checking_assert (fndecl && fndecl_built_in_p (fndecl, BUILT_IN_MD)= ); > int n_args =3D gimple_call_num_args (stmt); > @@ -18555,7 +18556,6 @@ ix86_gimple_fold_builtin (gimple_stmt_iterator *g= si) > { > loc =3D gimple_location (stmt); > tree type =3D TREE_TYPE (arg2); > - gimple_seq stmts =3D NULL; > if (VECTOR_FLOAT_TYPE_P (type)) > { > tree itype =3D GET_MODE_INNER (TYPE_MODE (type)) =3D=3D E_S= Fmode > @@ -18610,7 +18610,6 @@ ix86_gimple_fold_builtin (gimple_stmt_iterator *g= si) > tree zero_vec =3D build_zero_cst (type); > tree minus_one_vec =3D build_minus_one_cst (type); > tree cmp_type =3D truth_type_for (type); > - gimple_seq stmts =3D NULL; > tree cmp =3D gimple_build (&stmts, tcode, cmp_type, arg0, arg1)= ; > gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); > g =3D gimple_build_assign (gimple_call_lhs (stmt), > @@ -18904,14 +18903,18 @@ ix86_gimple_fold_builtin (gimple_stmt_iterator = *gsi) > break; > > case IX86_BUILTIN_PABSB: > + case IX86_BUILTIN_PABSW: > + case IX86_BUILTIN_PABSD: > + /* 64-bit vector abs2 is only supported under TARGET_MMX_WIT= H_SSE. */ > + if (!TARGET_64BIT) This should be !TARGET_MMX_WITH_SSE. TARGET_64BIT is not enough, see the definition of T_M_W_S in i386.h. OTOH, these builtins are available for TARGET_MMX, so I'm not sure if the above check is needed at all. Uros. > + break; > + /* FALLTHRU. */ > case IX86_BUILTIN_PABSB128: > case IX86_BUILTIN_PABSB256: > case IX86_BUILTIN_PABSB512: > - case IX86_BUILTIN_PABSW: > case IX86_BUILTIN_PABSW128: > case IX86_BUILTIN_PABSW256: > case IX86_BUILTIN_PABSW512: > - case IX86_BUILTIN_PABSD: > case IX86_BUILTIN_PABSD128: > case IX86_BUILTIN_PABSD256: > case IX86_BUILTIN_PABSD512: > @@ -18933,9 +18936,36 @@ ix86_gimple_fold_builtin (gimple_stmt_iterator *= gsi) > if (n_args > 1 > && !ix86_masked_all_ones (elems, gimple_call_arg (stmt, n_args = - 1))) > break; > - loc =3D gimple_location (stmt); > - g =3D gimple_build_assign (gimple_call_lhs (stmt), ABS_EXPR, arg0)= ; > - gsi_replace (gsi, g, false); > + { > + tree utype, ures, vce; > + switch (GET_MODE_INNER (TYPE_MODE (TREE_TYPE (arg0)))) > + { > + case E_QImode: > + utype =3D unsigned_intQI_type_node; > + break; > + case E_HImode: > + utype =3D unsigned_intHI_type_node; > + break; > + case E_SImode: > + utype =3D unsigned_intSI_type_node; > + break; > + case E_DImode: > + utype =3D long_long_unsigned_type_node; > + break; > + default: > + gcc_unreachable (); > + } > + utype =3D get_same_sized_vectype (utype, TREE_TYPE (arg0)); > + /* PABSB/W/D/Q store the unsigned result in dst, use ABSU_EXPR > + instead of ABS_EXPR to hanlde overflow case(TYPE_MIN). */ > + ures =3D gimple_build (&stmts, ABSU_EXPR, utype, arg0); > + gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); > + loc =3D gimple_location (stmt); > + vce =3D build1 (VIEW_CONVERT_EXPR, TREE_TYPE (arg0), ures); > + g =3D gimple_build_assign (gimple_call_lhs (stmt), > + VIEW_CONVERT_EXPR, vce); > + gsi_replace (gsi, g, false); > + } > return true; > > default: > diff --git a/gcc/testsuite/gcc.target/i386/pr110108.c b/gcc/testsuite/gcc= .target/i386/pr110108.c > new file mode 100644 > index 00000000000..cd05763b9bf > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/pr110108.c > @@ -0,0 +1,16 @@ > +/* { dg-do compile } */ > +/* { dg-options "-mavx2 -O2" } */ > +/* { dg-final { scan-assembler-times "vpblendvb" 2 } } */ > +#include > + > +__m128i do_stuff_128(__m128i X0, __m128i X1) { > + __m128i AbsX0 =3D _mm_abs_epi8(X0); > + __m128i Result =3D _mm_blendv_epi8(AbsX0, X1, AbsX0); > + return Result; > +} > + > +__m256i do_stuff_256(__m256i X0, __m256i X1) { > + __m256i AbsX0 =3D _mm256_abs_epi8(X0); > + __m256i Result =3D _mm256_blendv_epi8(AbsX0, X1, AbsX0); > + return Result; > +} > -- > 2.39.1.388.g2fc9e9ca3c >