From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <gcc-patches-return-305019-listarch-gcc-patches=gcc.gnu.org@gcc.gnu.org>
Received: (qmail 20139 invoked by alias); 20 Oct 2011 06:03:38 -0000
Received: (qmail 20125 invoked by uid 22791); 20 Oct 2011 06:03:34 -0000
X-SWARE-Spam-Status: No, hits=-2.3 required=5.0	tests=AWL,BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW
X-Spam-Check-By: sourceware.org
Received: from mail-yx0-f175.google.com (HELO mail-yx0-f175.google.com) (209.85.213.175)    by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 20 Oct 2011 06:03:20 +0000
Received: by yxj20 with SMTP id 20so193292yxj.20        for <gcc-patches@gcc.gnu.org>; Wed, 19 Oct 2011 23:03:19 -0700 (PDT)
MIME-Version: 1.0
Received: by 10.150.60.10 with SMTP id i10mr5930034yba.77.1319090599451; Wed, 19 Oct 2011 23:03:19 -0700 (PDT)
Received: by 10.146.82.5 with HTTP; Wed, 19 Oct 2011 23:03:19 -0700 (PDT)
In-Reply-To: <CAGs3RfsYMWBh5u2gYhS=C9GWjgPr39ONrA3Bsbgx7hQp+vh8gQ@mail.gmail.com>
References: <CAGs3RfsRA3sKRUNhj2ABqvPm+HTXGga9rA=ZfgXL3YWaPVF+Gw@mail.gmail.com>	<CAFULd4Yf478LBLh+NgyVqvHsPVAFM=uaQ1e2jbZ0PLgT2Ny4-Q@mail.gmail.com>	<CAMe9rOo+gf6UbzDnV7vJ4Fin8cNasCUu6i9NfZ+mejH9a0Dy7A@mail.gmail.com>	<CAGs3RfsYMWBh5u2gYhS=C9GWjgPr39ONrA3Bsbgx7hQp+vh8gQ@mail.gmail.com>
Date: Thu, 20 Oct 2011 07:43:00 -0000
Message-ID: <CAFULd4bxMpswp6sRi9AL-aXFus5J_+9p86UN2PxeyTVhrkyDTw@mail.gmail.com>
Subject: Re: [PATCH, i386, PR50766] Fix incorrect mem/reg operands order
From: Uros Bizjak <ubizjak@gmail.com>
To: Kirill Yukhin <kirill.yukhin@gmail.com>
Cc: "H.J. Lu" <hjl.tools@gmail.com>, gcc-patches List <gcc-patches@gcc.gnu.org>
Content-Type: text/plain; charset=ISO-8859-1
Content-Transfer-Encoding: quoted-printable
Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm
Precedence: bulk
List-Id: <gcc-patches.gcc.gnu.org>
List-Archive: <http://gcc.gnu.org/ml/gcc-patches/>
List-Post: <mailto:gcc-patches@gcc.gnu.org>
List-Help: <mailto:gcc-patches-help@gcc.gnu.org>
Sender: gcc-patches-owner@gcc.gnu.org
X-SW-Source: 2011-10/txt/msg01817.txt.bz2

On Thu, Oct 20, 2011 at 6:39 AM, Kirill Yukhin <kirill.yukhin@gmail.com> wr=
ote:

> Updated patch is attached. Test fails wihout and passing with the fix.
>
> ChangeLog entry:
> 2011-10-20 =A0Kirill Yukhin =A0<kirill.yukhin@intel.com>
>
> =A0 =A0 =A0 =A0PR target/50766
> =A0 =A0 =A0 =A0* config/i386/i386.md (bmi_bextr_<mode>): Update register/
> =A0 =A0 =A0 =A0memory operand order.
> =A0 =A0 =A0 =A0(bmi2_bzhi_<mode>3): Ditto.
> =A0 =A0 =A0 =A0(bmi2_pdep_<mode>3): Ditto.
> =A0 =A0 =A0 =A0(bmi2_pext_<mode>3): Ditto.
>
> testsuite/ChangeLog entry:
> 2011-10-20 =A0Kirill Yukhin =A0<kirill.yukhin@intel.com>
>
> =A0 =A0 =A0 =A0PR target/50766
> =A0 =A0 =A0 =A0* gcc.target/i386/pr50766.c: New test.
>
> Could you please have a look?

OK.

Thanks,
Uros.