From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qk1-x730.google.com (mail-qk1-x730.google.com [IPv6:2607:f8b0:4864:20::730]) by sourceware.org (Postfix) with ESMTPS id 240403858C52 for ; Wed, 20 Jul 2022 07:18:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 240403858C52 Received: by mail-qk1-x730.google.com with SMTP id e16so9112822qka.5 for ; Wed, 20 Jul 2022 00:18:24 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=CU/ec1/b9BIkiyEZGoY6ERj/OmN7MMNLFy6epA2dmtM=; b=lqrARndsxeUWYD+hVwmcXGv/ScSLsDptlFFu087yHLyr51FtSKqAXMxiuv62JRxB3l VTyW91iRgdyjZQQzOHsxW8sIWSuheQ1as34tLZEqUvVPp6lGmNxL7DT5GrM5qq7BetKM UWnqlboLTEO2PYK6NhnH7izH6FlEWrnpyRvkKgBkhLdUXHF04cNWnjMADA0n99LPPrL8 N25T2imgw06m5stdoMjgMreiZ3povX16ZHbuEUpfKGUcsESEVdPdc30f15DVA+VUQZEy HNznekcder2bhLNukNPxmgQ3yZjTvdIUlSU/NvnaAxNIb+sO2okvCfqytMrwED5viJR8 k+dA== X-Gm-Message-State: AJIora9d9zydas0yio5QAoFEHMnomyHbACwIsdfG5Ganzoab3HLZn2uZ 5dgZo3jEIbmeB1ETGYXPGSs6bI/BDY2XLOsTcZg= X-Google-Smtp-Source: AGRyM1vH3WI7TM5Raos3vVN0tk8rVqJL2EO6i18AEu8M9Z9f//Y3u8S7B8e7kD8oNlWXnxpUdZRFH4u7o6F9QwUWhn4= X-Received: by 2002:a05:620a:4007:b0:6b5:d88b:6d42 with SMTP id h7-20020a05620a400700b006b5d88b6d42mr13587372qko.180.1658301503431; Wed, 20 Jul 2022 00:18:23 -0700 (PDT) MIME-Version: 1.0 References: <20220719060736.18399-1-hongtao.liu@intel.com> In-Reply-To: From: Uros Bizjak Date: Wed, 20 Jul 2022 09:18:11 +0200 Message-ID: Subject: Re: [PATCH V2] Extend 16/32-bit vector bit_op patterns with (m, 0, i) alternative. To: Hongtao Liu Cc: liuhongt , "gcc-patches@gcc.gnu.org" Content-Type: multipart/mixed; boundary="0000000000000b19cf05e4376852" X-Spam-Status: No, score=-8.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, WEIRD_PORT autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Jul 2022 07:18:26 -0000 --0000000000000b19cf05e4376852 Content-Type: text/plain; charset="UTF-8" On Wed, Jul 20, 2022 at 8:54 AM Hongtao Liu wrote: > > On Wed, Jul 20, 2022 at 2:18 PM Uros Bizjak wrote: > > > > On Wed, Jul 20, 2022 at 8:14 AM Uros Bizjak wrote: > > > > > > On Wed, Jul 20, 2022 at 4:37 AM Hongtao Liu wrote: > > > > > > > > On Tue, Jul 19, 2022 at 5:37 PM Uros Bizjak wrote: > > > > > > > > > > On Tue, Jul 19, 2022 at 8:56 AM Hongtao Liu wrote: > > > > > > > > > > > > On Tue, Jul 19, 2022 at 2:35 PM Uros Bizjak via Gcc-patches > > > > > > wrote: > > > > > > > > > > > > > > On Tue, Jul 19, 2022 at 8:07 AM liuhongt wrote: > > > > > > > > > > > > > > > > And split it after reload. > > > > > > > > > > > > > > > > > You will need ix86_binary_operator_ok insn constraint here with > > > > > > > > > corresponding expander using ix86_fixup_binary_operands_no_copy to > > > > > > > > > prepare insn operands. > > > > > > > > Split define_expand with just register_operand, and allow > > > > > > > > memory/immediate in define_insn, assume combine/forwprop will do optimization. > > > > > > > > > > > > > > But you will *ease* the job of the above passes if you use > > > > > > > ix86_fixup_binary_operands_no_copy in the expander. > > > > > > for -m32, it will hit ICE in > > > > > > Breakpoint 1, ix86_fixup_binary_operands_no_copy (code=XOR, > > > > > > mode=E_V4QImode, operands=0x7fffffffa970) a > > > > > > /gcc/config/i386/i386-expand.cc:1184 > > > > > > 1184 rtx dst = ix86_fixup_binary_operands (code, mode, operands); > > > > > > (gdb) n > > > > > > 1185 gcc_assert (dst == operands[0]); -- here > > > > > > (gdb) > > > > > > > > > > > > the original operands[0], operands[1], operands[2] are below > > > > > > (gdb) p debug_rtx (operands[0]) > > > > > > (mem/c:V4QI (plus:SI (reg/f:SI 77 virtual-stack-vars) > > > > > > (const_int -8220 [0xffffffffffffdfe4])) [0 MEM > > > > > unsigned char> [(unsigned char *)&tmp2 + 4B]+0 S4 A32]) > > > > > > $1 = void > > > > > > (gdb) p debug_rtx (operands[1]) > > > > > > (subreg:V4QI (reg:SI 129) 0) > > > > > > $2 = void > > > > > > (gdb) p debug_rtx (operands[2]) > > > > > > (subreg:V4QI (reg:SI 98 [ _46 ]) 0) > > > > > > $3 = void > > > > > > (gdb) > > > > > > > > > > > > since operands[0] is mem and not equal to operands[1], > > > > > > ix86_fixup_binary_operands will create a pseudo register for dst. and > > > > > > then hit ICE. > > > > > > Is this a bug or assumed? > > > > > > > > > > You will need ix86_expand_binary_operator here. > > > > It will swap memory operand from op1 to op2 and hit ICE for unrecognized insn. > > > > > > > > What about this? > > > > > > Still no good... You are using commutative operands, so the predicate > > > of operand 2 should also allow memory. So, the predicate should be > > > nonimmediate_or_x86_64_const_vector_operand. The intermediate insn > > > pattern should look something like *_1, but with > > > added XMM and MMX reg alternatives instead of mask regs. > > > > Alternatively, you can use UNKNOWN operator to prevent > > canonicalization, but then you should not use commutative constraint > > in the intermediate insn. I think this is the best solution. > Like this? Please check the attached (lightly tested) patch that keeps commutative operands. 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